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author | Chris Lattner <sabre@nondot.org> | 2009-03-24 15:22:11 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2009-03-24 15:22:11 +0000 |
commit | fc9d161f16933498d572463edf952c03bc5b1ec0 (patch) | |
tree | e19352b889abd17602888b992934305846039e0d /lib | |
parent | a96dc14968ded9d4cff2382696cfdb6e40173e8a (diff) | |
download | external_llvm-fc9d161f16933498d572463edf952c03bc5b1ec0.zip external_llvm-fc9d161f16933498d572463edf952c03bc5b1ec0.tar.gz external_llvm-fc9d161f16933498d572463edf952c03bc5b1ec0.tar.bz2 |
simplify this code a bit now that "allocation to a vreg class" can never
fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67616 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 90ebc4a..49e6744 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -4929,9 +4929,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // Otherwise, if this was a reference to an LLVM register class, create vregs // for this reference. - std::vector<unsigned> RegClassRegs; - const TargetRegisterClass *RC = PhysReg.second; - if (RC) { + if (PhysReg.second != 0) { RegVT = *PhysReg.second->vt_begin(); if (OpInfo.ConstraintVT == MVT::Other) ValueVT = RegVT; @@ -4943,13 +4941,14 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); return; - } else { - // This is a reference to a register class that doesn't directly correspond - // to an LLVM register class. Allocate NumRegs consecutive, available, - // registers from the class. - RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, - OpInfo.ConstraintVT); } + + // This is a reference to a register class that doesn't directly correspond + // to an LLVM register class. Allocate NumRegs consecutive, available, + // registers from the class. + std::vector<unsigned> RegClassRegs + = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, + OpInfo.ConstraintVT); const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); unsigned NumAllocated = 0; @@ -4965,13 +4964,11 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // Check to see if this register is allocatable (i.e. don't give out the // stack pointer). - if (RC == 0) { - RC = isAllocatableRegister(Reg, MF, TLI, TRI); - if (!RC) { // Couldn't allocate this register. - // Reset NumAllocated to make sure we return consecutive registers. - NumAllocated = 0; - continue; - } + const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); + if (!RC) { // Couldn't allocate this register. + // Reset NumAllocated to make sure we return consecutive registers. + NumAllocated = 0; + continue; } // Okay, this register is good, we can use it. |