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author | Shih-wei Liao <sliao@google.com> | 2010-06-04 12:34:56 -0700 |
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committer | Shih-wei Liao <sliao@google.com> | 2010-06-04 12:34:56 -0700 |
commit | 8a54f3e1f79c1e57e76a1cc53c6c5697374ea7b5 (patch) | |
tree | 9a9ff3c18a33cf3838b1e37813f7ef9fe64d2e78 /llvm-tblgen-rules.mk | |
parent | ee9f5c0a63197e6e3148f09b401f0056cdf1a179 (diff) | |
download | external_llvm-8a54f3e1f79c1e57e76a1cc53c6c5697374ea7b5.zip external_llvm-8a54f3e1f79c1e57e76a1cc53c6c5697374ea7b5.tar.gz external_llvm-8a54f3e1f79c1e57e76a1cc53c6c5697374ea7b5.tar.bz2 |
Initial slang.
Change-Id: I4f84a741e5fbc440cd4c251406d2b611a237f713
Diffstat (limited to 'llvm-tblgen-rules.mk')
-rw-r--r-- | llvm-tblgen-rules.mk | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk new file mode 100644 index 0000000..a3d71cb --- /dev/null +++ b/llvm-tblgen-rules.mk @@ -0,0 +1,116 @@ +########################################################### +## Commands for running tblgen to compile a td file +########################################################## +define transform-td-to-out +$(if $(LOCAL_IS_HOST_MODULE), \ + $(call transform-host-td-to-out,$(1)), \ + $(call transform-device-td-to-out,$(1))) +endef + +########################################################### +## TableGen: Compile .td files to .inc. +########################################################### + +# Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require +# for macro local-intermediates-dir) +ifeq ($(LOCAL_MODULE_CLASS),) + LOCAL_MODULE_CLASS := STATIC_LIBRARIES +endif + +ifneq ($(strip $(TBLGEN_TABLES)),) + +intermediates := $(call local-intermediates-dir) +tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES)) +LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables) + +tblgen_source_dir := $(LOCAL_PATH) +ifneq ($(TBLGEN_TD_DIR),) +tblgen_source_dir := $(TBLGEN_TD_DIR) +endif + +ifneq ($(filter %GenRegisterNames.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenRegisterNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,register-enums) +endif + +ifneq ($(filter %GenRegisterInfo.h.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenRegisterInfo.h.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,register-desc-header) +endif + +ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,register-desc) +endif + +ifneq ($(filter %GenInstrNames.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenInstrNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,instr-enums) +endif + +ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,instr-desc) +endif + +ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,asm-writer) +endif + +ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,asm-writer -asmwriternum=1) +endif + +ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,asm-matcher) +endif + +ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,emitter) +endif + +ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,dag-isel) +endif + +ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,disassembler) +endif + +ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,enhanced-disassembly-info) +endif + +ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,fast-isel) +endif + +ifneq ($(filter %GenSubtarget.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenSubtarget.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,subtarget) +endif + +ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,callingconv) +endif + +ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN) + $(call transform-td-to-out,tgt_intrinsics) +endif + +ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),) +$(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN) + $(call transform-td-to-out,arm-decoder) +endif + +endif |