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authorChris Lattner <sabre@nondot.org>2003-08-03 17:24:20 +0000
committerChris Lattner <sabre@nondot.org>2003-08-03 17:24:20 +0000
commit169e66bfc23c20a3df7d0364f5f1abb43f33694b (patch)
tree2e36cb25518c7a350179bfcd85ac97967f4de0b3 /support/tools/TableGen
parent33ccf7edff6d784c7f6ea85ada2b67062272073e (diff)
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Add support for instruction enum emission
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7516 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'support/tools/TableGen')
-rw-r--r--support/tools/TableGen/TableGen.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/support/tools/TableGen/TableGen.cpp b/support/tools/TableGen/TableGen.cpp
index 1d8b60b..990e2b3 100644
--- a/support/tools/TableGen/TableGen.cpp
+++ b/support/tools/TableGen/TableGen.cpp
@@ -14,6 +14,7 @@
#include "Support/FileUtilities.h"
#include "CodeEmitterGen.h"
#include "RegisterInfoEmitter.h"
+#include "InstrInfoEmitter.h"
#include <algorithm>
#include <fstream>
@@ -21,6 +22,7 @@ enum ActionType {
PrintRecords,
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
+ GenInstrEnums,
PrintEnums,
Parse,
};
@@ -38,6 +40,8 @@ namespace {
"Generate a register info description"),
clEnumValN(GenRegisterHeader, "gen-register-desc-header",
"Generate a register info description header"),
+ clEnumValN(GenInstrEnums, "gen-instr-enums",
+ "Generate enum values for instructions"),
clEnumValN(PrintEnums, "print-enums",
"Print enum values for a class"),
clEnumValN(Parse, "parse",
@@ -417,6 +421,7 @@ int main(int argc, char **argv) {
case GenEmitter:
CodeEmitterGen(Records).run(*Out);
break;
+
case GenRegisterEnums:
RegisterInfoEmitter(Records).runEnums(*Out);
break;
@@ -426,6 +431,11 @@ int main(int argc, char **argv) {
case GenRegisterHeader:
RegisterInfoEmitter(Records).runHeader(*Out);
break;
+
+ case GenInstrEnums:
+ InstrInfoEmitter(Records).runEnums(*Out);
+ break;
+
case PrintEnums:
std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
for (unsigned i = 0, e = Recs.size(); i != e; ++i)