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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/Analysis/CostModel/X86/testshiftshl.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/Analysis/CostModel/X86/testshiftshl.ll')
| -rw-r--r-- | test/Analysis/CostModel/X86/testshiftshl.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll index 40effd0..c36e0f5 100644 --- a/test/Analysis/CostModel/X86/testshiftshl.ll +++ b/test/Analysis/CostModel/X86/testshiftshl.ll @@ -7,7 +7,7 @@ entry: ; SSE2: shift2i16 ; SSE2: cost of 20 {{.*}} shl ; SSE2-CODEGEN: shift2i16 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype %a , %b ret %shifttype %0 @@ -67,7 +67,7 @@ entry: ; SSE2: shift2i32 ; SSE2: cost of 20 {{.*}} shl ; SSE2-CODEGEN: shift2i32 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype2i32 %a , %b ret %shifttype2i32 %0 @@ -127,7 +127,7 @@ entry: ; SSE2: shift2i64 ; SSE2: cost of 20 {{.*}} shl ; SSE2-CODEGEN: shift2i64 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype2i64 %a , %b ret %shifttype2i64 %0 @@ -139,7 +139,7 @@ entry: ; SSE2: shift4i64 ; SSE2: cost of 40 {{.*}} shl ; SSE2-CODEGEN: shift4i64 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype4i64 %a , %b ret %shifttype4i64 %0 @@ -151,7 +151,7 @@ entry: ; SSE2: shift8i64 ; SSE2: cost of 80 {{.*}} shl ; SSE2-CODEGEN: shift8i64 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype8i64 %a , %b ret %shifttype8i64 %0 @@ -163,7 +163,7 @@ entry: ; SSE2: shift16i64 ; SSE2: cost of 160 {{.*}} shl ; SSE2-CODEGEN: shift16i64 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype16i64 %a , %b ret %shifttype16i64 %0 @@ -175,7 +175,7 @@ entry: ; SSE2: shift32i64 ; SSE2: cost of 320 {{.*}} shl ; SSE2-CODEGEN: shift32i64 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype32i64 %a , %b ret %shifttype32i64 %0 @@ -187,7 +187,7 @@ entry: ; SSE2: shift2i8 ; SSE2: cost of 20 {{.*}} shl ; SSE2-CODEGEN: shift2i8 - ; SSE2-CODEGEN: shlq %cl + ; SSE2-CODEGEN: psllq %0 = shl %shifttype2i8 %a , %b ret %shifttype2i8 %0 |