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authorJoel Jones <joel_k_jones@apple.com>2012-07-18 00:02:16 +0000
committerJoel Jones <joel_k_jones@apple.com>2012-07-18 00:02:16 +0000
commit7c82e6a32a84e238c9e4e57dd43eaba540a79ce1 (patch)
treeee690b3fa0c29940515aa6a66214f8190b7fc180 /test/Bitcode
parent0b5f1aca32076e9a29dc3d716945d1ec6003c96e (diff)
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More replacing of target-dependent intrinsics with target-indepdent
intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Bitcode')
-rw-r--r--test/Bitcode/arm32_neon_vcnt_upgrade.ll11
1 files changed, 10 insertions, 1 deletions
diff --git a/test/Bitcode/arm32_neon_vcnt_upgrade.ll b/test/Bitcode/arm32_neon_vcnt_upgrade.ll
index b3f2f03..10b9284 100644
--- a/test/Bitcode/arm32_neon_vcnt_upgrade.ll
+++ b/test/Bitcode/arm32_neon_vcnt_upgrade.ll
@@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; NB: currently tests only vclz, should also test vcnt and vcls
+; Tests vclz and vcnt
define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
;CHECK: @vclz16
@@ -9,4 +9,13 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
ret <4 x i16> %tmp2
}
+define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+;CHECK: @vcnt8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
+;CHECK: call <8 x i8> @llvm.ctpop.v8i8(<8 x i8>
+ ret <8 x i8> %tmp2
+}
+
declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone