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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/AArch64/arm64-fast-isel-conversion.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/AArch64/arm64-fast-isel-conversion.ll')
| -rw-r--r-- | test/CodeGen/AArch64/arm64-fast-isel-conversion.ll | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll b/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll index e515184..1b68865 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s ;; Test various conversions. define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp { @@ -27,16 +27,16 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %tmp = load i64* %d.addr, align 8 + %tmp = load i64, i64* %d.addr, align 8 %conv = trunc i64 %tmp to i32 store i32 %conv, i32* %c.addr, align 4 - %tmp1 = load i32* %c.addr, align 4 + %tmp1 = load i32, i32* %c.addr, align 4 %conv2 = trunc i32 %tmp1 to i16 store i16 %conv2, i16* %b.addr, align 2 - %tmp3 = load i16* %b.addr, align 2 + %tmp3 = load i16, i16* %b.addr, align 2 %conv4 = trunc i16 %tmp3 to i8 store i8 %conv4, i8* %a.addr, align 1 - %tmp5 = load i8* %a.addr, align 1 + %tmp5 = load i8, i8* %a.addr, align 1 %conv6 = zext i8 %tmp5 to i32 ret i32 %conv6 } @@ -66,16 +66,16 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %tmp = load i8* %a.addr, align 1 + %tmp = load i8, i8* %a.addr, align 1 %conv = zext i8 %tmp to i16 store i16 %conv, i16* %b.addr, align 2 - %tmp1 = load i16* %b.addr, align 2 + %tmp1 = load i16, i16* %b.addr, align 2 %conv2 = zext i16 %tmp1 to i32 store i32 %conv2, i32* %c.addr, align 4 - %tmp3 = load i32* %c.addr, align 4 + %tmp3 = load i32, i32* %c.addr, align 4 %conv4 = zext i32 %tmp3 to i64 store i64 %conv4, i64* %d.addr, align 8 - %tmp5 = load i64* %d.addr, align 8 + %tmp5 = load i64, i64* %d.addr, align 8 ret i64 %tmp5 } @@ -121,16 +121,16 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %tmp = load i8* %a.addr, align 1 + %tmp = load i8, i8* %a.addr, align 1 %conv = sext i8 %tmp to i16 store i16 %conv, i16* %b.addr, align 2 - %tmp1 = load i16* %b.addr, align 2 + %tmp1 = load i16, i16* %b.addr, align 2 %conv2 = sext i16 %tmp1 to i32 store i32 %conv2, i32* %c.addr, align 4 - %tmp3 = load i32* %c.addr, align 4 + %tmp3 = load i32, i32* %c.addr, align 4 %conv4 = sext i32 %tmp3 to i64 store i64 %conv4, i64* %d.addr, align 8 - %tmp5 = load i64* %d.addr, align 8 + %tmp5 = load i64, i64* %d.addr, align 8 ret i64 %tmp5 } @@ -409,7 +409,7 @@ define void @stack_trunc() nounwind { ; CHECK: add sp, sp, #16 %a = alloca i8, align 1 %b = alloca i64, align 8 - %c = load i64* %b, align 8 + %c = load i64, i64* %b, align 8 %d = trunc i64 %c to i8 store i8 %d, i8* %a, align 1 ret void |