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authorStephen Hines <srhines@google.com>2014-05-29 02:49:00 -0700
committerStephen Hines <srhines@google.com>2014-05-29 02:49:00 -0700
commitdce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch)
treedcebc53f2b182f145a2e659393bf9a0472cedf23 /test/CodeGen/AArch64/arm64-icmp-opt.ll
parent220b921aed042f9e520c26cffd8282a94c66c3d5 (diff)
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Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/CodeGen/AArch64/arm64-icmp-opt.ll')
-rw-r--r--test/CodeGen/AArch64/arm64-icmp-opt.ll17
1 files changed, 17 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/arm64-icmp-opt.ll b/test/CodeGen/AArch64/arm64-icmp-opt.ll
new file mode 100644
index 0000000..7b12ed7
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-icmp-opt.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=arm64 | FileCheck %s
+
+; Optimize (x > -1) to (x >= 0) etc.
+; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
+; for comparison only
+; rdar://10233472
+
+define i32 @t1(i64 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: t1:
+; CHECK-NOT: movn
+; CHECK: cmp x0, #0
+; CHECK: cset w0, ge
+ %cmp = icmp sgt i64 %a, -1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}