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author | Bill Wendling <isanbard@gmail.com> | 2013-11-26 13:35:26 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2013-11-26 13:35:26 +0000 |
commit | f38d6740c6532c452983731521b8323d75fc4745 (patch) | |
tree | 319d81f1083a6d236b797c90fee63b7788de9501 /test/CodeGen/AArch64/neon-copy.ll | |
parent | c23b3b05499f4518c64a953eea0a2496739e6d24 (diff) | |
download | external_llvm-f38d6740c6532c452983731521b8323d75fc4745.zip external_llvm-f38d6740c6532c452983731521b8323d75fc4745.tar.gz external_llvm-f38d6740c6532c452983731521b8323d75fc4745.tar.bz2 |
Merging r195424:
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r195424 | haoliu | 2013-11-22 00:47:22 -0800 (Fri, 22 Nov 2013) | 4 lines
Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected.
"%tmp = bitcast i64 %in to <2 x i32>" can't be selected.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195764 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/neon-copy.ll')
-rw-r--r-- | test/CodeGen/AArch64/neon-copy.ll | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/neon-copy.ll b/test/CodeGen/AArch64/neon-copy.ll index e1afc24..e18530e 100644 --- a/test/CodeGen/AArch64/neon-copy.ll +++ b/test/CodeGen/AArch64/neon-copy.ll @@ -530,3 +530,86 @@ define <2 x i64> @test_vdupq_laneq_s64(<2 x i64> %v1) #0 { ret <2 x i64> %shuffle } +define i64 @test_bitcastv8i8toi64(<8 x i8> %in) { +; CHECK-LABEL: test_bitcastv8i8toi64: + %res = bitcast <8 x i8> %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define i64 @test_bitcastv4i16toi64(<4 x i16> %in) { +; CHECK-LABEL: test_bitcastv4i16toi64: + %res = bitcast <4 x i16> %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define i64 @test_bitcastv2i32toi64(<2 x i32> %in) { +; CHECK-LABEL: test_bitcastv2i32toi64: + %res = bitcast <2 x i32> %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define i64 @test_bitcastv2f32toi64(<2 x float> %in) { +; CHECK-LABEL: test_bitcastv2f32toi64: + %res = bitcast <2 x float> %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define i64 @test_bitcastv1i64toi64(<1 x i64> %in) { +; CHECK-LABEL: test_bitcastv1i64toi64: + %res = bitcast <1 x i64> %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define i64 @test_bitcastv1f64toi64(<1 x double> %in) { +; CHECK-LABEL: test_bitcastv1f64toi64: + %res = bitcast <1 x double> %in to i64 +; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} + ret i64 %res +} + +define <8 x i8> @test_bitcasti64tov8i8(i64 %in) { +; CHECK-LABEL: test_bitcasti64tov8i8: + %res = bitcast i64 %in to <8 x i8> +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret <8 x i8> %res +} + +define <4 x i16> @test_bitcasti64tov4i16(i64 %in) { +; CHECK-LABEL: test_bitcasti64tov4i16: + %res = bitcast i64 %in to <4 x i16> +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret <4 x i16> %res +} + +define <2 x i32> @test_bitcasti64tov2i32(i64 %in) { +; CHECK-LABEL: test_bitcasti64tov2i32: + %res = bitcast i64 %in to <2 x i32> +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret <2 x i32> %res +} + +define <2 x float> @test_bitcasti64tov2f32(i64 %in) { +; CHECK-LABEL: test_bitcasti64tov2f32: + %res = bitcast i64 %in to <2 x float> +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret <2 x float> %res +} + +define <1 x i64> @test_bitcasti64tov1i64(i64 %in) { +; CHECK-LABEL: test_bitcasti64tov1i64: + %res = bitcast i64 %in to <1 x i64> +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret <1 x i64> %res +} + +define <1 x double> @test_bitcasti64tov1f64(i64 %in) { +; CHECK-LABEL: test_bitcasti64tov1f64: + %res = bitcast i64 %in to <1 x double> +; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} + ret <1 x double> %res +}
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