Test case hygiene.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176772 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 16 insertions, 16 deletions

diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll
index 9dddf74..c66aa5b 100644
--- a/test/CodeGen/AArch64/callee-save.ll
+++ b/test/CodeGen/AArch64/callee-save.ll
@@ -5,10 +5,10 @@
 define void @foo() {
 ; CHECK: foo:
 
-; CHECK stp d14, d15, [sp
-; CHECK stp d12, d13, [sp
-; CHECK stp d10, d11, [sp
-; CHECK stp d8, d9, [sp
+; CHECK: stp d14, d15, [sp
+; CHECK: stp d12, d13, [sp
+; CHECK: stp d10, d11, [sp
+; CHECK: stp d8, d9, [sp
 
   ; Create lots of live variables to exhaust the supply of
   ; caller-saved registers
diff --git a/test/CodeGen/AArch64/fastcc-reserved.ll b/test/CodeGen/AArch64/fastcc-reserved.ll
index 1a114a5..e40aa30 100644
--- a/test/CodeGen/AArch64/fastcc-reserved.ll
+++ b/test/CodeGen/AArch64/fastcc-reserved.ll
@@ -13,7 +13,7 @@ define fastcc void @foo(i32 %in) {
 
 ; Normal frame setup stuff:
 ; CHECK: sub sp, sp,
-; CHECK stp x29, x30
+; CHECK: stp x29, x30
 
 ; Reserve space for call-frame:
 ; CHECK: sub sp, sp, #16
@@ -38,17 +38,17 @@ define void @foo1(i32 %in) {
 
   %addr = alloca i8, i32 %in
 ; Normal frame setup again
-; CHECK sub sp, sp,
-; CHECK stp x29, x30
+; CHECK: sub sp, sp,
+; CHECK: stp x29, x30
 
 ; Reserve space for call-frame
-; CHECK sub sp, sp, #16
+; CHECK: sub sp, sp, #16
 
   call void @wont_pop([8 x i32] undef, i32 42)
-; CHECK bl wont_pop
+; CHECK: bl wont_pop
 
 ; This time we *do* need to unreserve the call-frame
-; CHECK add sp, sp, #16
+; CHECK: add sp, sp, #16
 
 ; Check for epilogue (primarily to make sure sp spotted above wasn't
 ; part of it).
diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll
index 5675e5a..78fde6a 100644
--- a/test/CodeGen/AArch64/func-argpassing.ll
+++ b/test/CodeGen/AArch64/func-argpassing.ll
@@ -44,7 +44,7 @@ define void @take_struct(%myStruct* byval %structval) {
     %val1 = load i64* %addr1
 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
     store i64 %val1, i64* @var64
-; CHECK str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
+; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
 
     ret void
 }
@@ -66,7 +66,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
     %val1 = load i64* %addr1
 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
     store i64 %val1, i64* @var64
-; CHECK str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
+; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
 
     ret void
 }
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index abb09a5..13b689c 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -61,7 +61,7 @@ define void @simple_rets() {
 
   call void @return_large_struct(%myStruct* sret @varstruct)
 ; CHECK: add x8, {{x[0-9]+}}, #:lo12:varstruct
-; CHECK bl return_large_struct
+; CHECK: bl return_large_struct
 
   ret void
 }
@@ -93,7 +93,7 @@ define void @check_stack_args() {
 ; CHECK: ldr s[[STACKEDREG:[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI
 ; CHECK: mov x0, sp
 ; CHECK: str d[[STACKEDREG]], [x0]
-; CHECK bl stacked_fpu
+; CHECK: bl stacked_fpu
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll
index afdf681..b8a5fb9 100644
--- a/test/CodeGen/AArch64/movw-consts.ll
+++ b/test/CodeGen/AArch64/movw-consts.ll
@@ -75,7 +75,7 @@ define i64 @test10() {
 
 define void @test11() {
 ; CHECK: test11:
-; CHECK movz {{w[0-9]+}}, #0
+; CHECK: mov {{w[0-9]+}}, wzr
   store i32 0, i32* @var32
   ret void
 }
diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
index 5c97a02..980e2ff 100644
--- a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
+++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
@@ -5,7 +5,7 @@ declare void @bar()
 
 define void @test_w29_reserved() {
 ; CHECK: test_w29_reserved:
-; CHECK add x29, sp, #{{[0-9]+}}
+; CHECK: add x29, sp, #{{[0-9]+}}
 
   %val1 = load volatile i32* @var
   %val2 = load volatile i32* @var