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| author | Bob Wilson <bob.wilson@apple.com> | 2010-09-10 05:15:04 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-09-10 05:15:04 +0000 |
| commit | bd9c766fa67f718f225e461ed69c3d11cfe7068c (patch) | |
| tree | 9023ab09a14db518e7347f48b47925049acd1471 /test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | |
| parent | 0cf9a820e435a74ef93930dcaf8917323f2f99be (diff) | |
| download | external_llvm-bd9c766fa67f718f225e461ed69c3d11cfe7068c.zip external_llvm-bd9c766fa67f718f225e461ed69c3d11cfe7068c.tar.gz external_llvm-bd9c766fa67f718f225e461ed69c3d11cfe7068c.tar.bz2 | |
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll')
| -rw-r--r-- | test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index 81483cb..ee63656 100644 --- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -1,11 +1,15 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] +; CHECK: dct_luma_sp: define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { entry: +; Make sure to use base-updating stores for saving callee-saved registers. +; CHECK-NOT: sub sp +; CHECK: vstmdb sp! %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] br label %cond_next489 |