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| author | Stephen Hines <srhines@google.com> | 2013-05-02 16:19:29 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2013-05-02 16:19:29 -0700 |
| commit | 38578c4919ea18ceb27e29988b2d857afe6215bf (patch) | |
| tree | 6718ee1e6a1a59f46b6c847439ebfcd291c1e393 /test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll | |
| parent | ffb69c62ac54b0af5768ae9486b93b39a6c6b94c (diff) | |
| parent | a7a05ee70cb07f32996a0587a636b406c746b71b (diff) | |
| download | external_llvm-38578c4919ea18ceb27e29988b2d857afe6215bf.zip external_llvm-38578c4919ea18ceb27e29988b2d857afe6215bf.tar.gz external_llvm-38578c4919ea18ceb27e29988b2d857afe6215bf.tar.bz2 | |
Merge remote-tracking branch 'upstream/master' into merge-20130502
Conflicts:
lib/Support/Unix/Signals.inc
unittests/Transforms/Utils/Cloning.cpp
Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
Diffstat (limited to 'test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll')
| -rw-r--r-- | test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll index e4ad45b..adb5c7e 100644 --- a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll +++ b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll @@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable %45 = fmul <4 x float> undef, undef %46 = fmul <4 x float> %45, %43 %47 = fmul <4 x float> undef, %44 - %48 = load <4 x float>* undef, align 8, !tbaa !1 + %48 = load <4 x float>* undef, align 8 %49 = bitcast <4 x float> %48 to <2 x i64> %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1> %51 = bitcast <1 x i64> %50 to <2 x float> @@ -145,10 +145,10 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable %61 = fmul <4 x float> %59, %60 %62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01> %63 = fadd <4 x float> %47, %62 - store <4 x float> %46, <4 x float>* undef, align 8, !tbaa !1 + store <4 x float> %46, <4 x float>* undef, align 8 call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind - store <4 x float> %63, <4 x float>* undef, align 8, !tbaa !1 + store <4 x float> %63, <4 x float>* undef, align 8 unreachable ; <label>:64 ; preds = %41, %40 @@ -170,5 +170,3 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable declare arm_aapcs_vfpcc void @bar(%0*, float) !0 = metadata !{metadata !"branch_weights", i32 64, i32 4} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} |