diff options
| author | Stephen Hines <srhines@google.com> | 2015-04-01 18:49:24 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2015-04-01 18:49:26 +0000 |
| commit | 3fa16bd6062e23bcdb82ed4dd965674792e6b761 (patch) | |
| tree | 9348fc507292f7e8715d22d64ce5a32131b4f875 /test/CodeGen/ARM/crc32.ll | |
| parent | beed47390a60f6f0c77532b3d3f76bb47ef49423 (diff) | |
| parent | ebe69fe11e48d322045d5949c83283927a0d790b (diff) | |
| download | external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.zip external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.tar.gz external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.tar.bz2 | |
Merge "Update aosp/master LLVM for rebase to r230699."
Diffstat (limited to 'test/CodeGen/ARM/crc32.ll')
| -rw-r--r-- | test/CodeGen/ARM/crc32.ll | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/crc32.ll b/test/CodeGen/ARM/crc32.ll new file mode 100644 index 0000000..cc94330 --- /dev/null +++ b/test/CodeGen/ARM/crc32.ll @@ -0,0 +1,58 @@ +; RUN: llc -mtriple=thumbv8 -o - %s | FileCheck %s + +define i32 @test_crc32b(i32 %cur, i8 %next) { +; CHECK-LABEL: test_crc32b: +; CHECK: crc32b r0, r0, r1 + %bits = zext i8 %next to i32 + %val = call i32 @llvm.arm.crc32b(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32h(i32 %cur, i16 %next) { +; CHECK-LABEL: test_crc32h: +; CHECK: crc32h r0, r0, r1 + %bits = zext i16 %next to i32 + %val = call i32 @llvm.arm.crc32h(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32w(i32 %cur, i32 %next) { +; CHECK-LABEL: test_crc32w: +; CHECK: crc32w r0, r0, r1 + %val = call i32 @llvm.arm.crc32w(i32 %cur, i32 %next) + ret i32 %val +} + +define i32 @test_crc32cb(i32 %cur, i8 %next) { +; CHECK-LABEL: test_crc32cb: +; CHECK: crc32cb r0, r0, r1 + %bits = zext i8 %next to i32 + %val = call i32 @llvm.arm.crc32cb(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32ch(i32 %cur, i16 %next) { +; CHECK-LABEL: test_crc32ch: +; CHECK: crc32ch r0, r0, r1 + %bits = zext i16 %next to i32 + %val = call i32 @llvm.arm.crc32ch(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32cw(i32 %cur, i32 %next) { +; CHECK-LABEL: test_crc32cw: +; CHECK: crc32cw r0, r0, r1 + %val = call i32 @llvm.arm.crc32cw(i32 %cur, i32 %next) + ret i32 %val +} + + +declare i32 @llvm.arm.crc32b(i32, i32) +declare i32 @llvm.arm.crc32h(i32, i32) +declare i32 @llvm.arm.crc32w(i32, i32) +declare i32 @llvm.arm.crc32x(i32, i64) + +declare i32 @llvm.arm.crc32cb(i32, i32) +declare i32 @llvm.arm.crc32ch(i32, i32) +declare i32 @llvm.arm.crc32cw(i32, i32) +declare i32 @llvm.arm.crc32cx(i32, i64) |