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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/ARM/fast-isel-load-store-verify.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/ARM/fast-isel-load-store-verify.ll')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-load-store-verify.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/fast-isel-load-store-verify.ll b/test/CodeGen/ARM/fast-isel-load-store-verify.ll index 710d88b..acf10c8 100644 --- a/test/CodeGen/ARM/fast-isel-load-store-verify.ll +++ b/test/CodeGen/ARM/fast-isel-load-store-verify.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL ; FIXME Add tests for thumbv7, they currently fail MI verification because ; of a mismatch in register classes in uses. @@ -17,7 +17,7 @@ define i8 @t1() nounwind uwtable ssp { ; ALL: @t1 ; ALL: ldrb ; ALL: add - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 %2 = add nsw i8 %1, 1 ret i8 %2 } @@ -26,7 +26,7 @@ define i16 @t2() nounwind uwtable ssp { ; ALL: @t2 ; ALL: ldrh ; ALL: add - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = add nsw i16 %1, 1 ret i16 %2 } @@ -35,7 +35,7 @@ define i32 @t3() nounwind uwtable ssp { ; ALL: @t3 ; ALL: ldr ; ALL: add - %1 = load i32* @c, align 4 + %1 = load i32, i32* @c, align 4 %2 = add nsw i32 %1, 1 ret i32 %2 } |