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author | Andrew Trick <atrick@apple.com> | 2013-04-24 15:54:43 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-04-24 15:54:43 +0000 |
commit | e38afe1e335084134f7830ba6f2208e2ddde59b4 (patch) | |
tree | e50d2dd8447a5d5d900d83d7c1b0f58c5090e61d /test/CodeGen/ARM/misched-copy-arm.ll | |
parent | e2326ad2c00fe3e8e21dbf312f1987ba92308733 (diff) | |
download | external_llvm-e38afe1e335084134f7830ba6f2208e2ddde59b4.zip external_llvm-e38afe1e335084134f7830ba6f2208e2ddde59b4.tar.gz external_llvm-e38afe1e335084134f7830ba6f2208e2ddde59b4.tar.bz2 |
MI Sched: eliminate local vreg copies.
For now, we just reschedule instructions that use the copied vregs and
let regalloc elliminate it. I would really like to eliminate the
copies on-the-fly during scheduling, but we need a complete
implementation of repairIntervalsInRange() first.
The general strategy is for the register coalescer to eliminate as
many global copies as possible and shrink live ranges to be
extended-basic-block local. The coalescer should not have to worry
about resolving local copies (e.g. it shouldn't attemp to reorder
instructions). The scheduler is a much better place to deal with local
interference. The coalescer side of this equation needs work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180193 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/misched-copy-arm.ll')
-rw-r--r-- | test/CodeGen/ARM/misched-copy-arm.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll new file mode 100644 index 0000000..4b15326 --- /dev/null +++ b/test/CodeGen/ARM/misched-copy-arm.ll @@ -0,0 +1,30 @@ +; REQUIRES: asserts +; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; +; Loop counter copies should be eliminated. +; There is also a MUL here, but we don't care where it is scheduled. +; CHECK: postinc +; CHECK: *** Final schedule for BB#2 *** +; CHECK: t2LDRs +; CHECK: t2ADDrr +; CHECK: t2CMPrr +; CHECK: COPY +define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind { +entry: + %cmp4 = icmp eq i32 %a, 0 + br i1 %cmp4, label %for.end, label %for.body + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ] + %indvars.iv.next = add i32 %indvars.iv, %s + %arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %mul = mul nsw i32 %0, %s.05 + %exitcond = icmp eq i32 %indvars.iv.next, %a + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ] + ret i32 %s.0.lcssa +} |