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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/ARM/swift-vldm.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/ARM/swift-vldm.ll')
| -rw-r--r-- | test/CodeGen/ARM/swift-vldm.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/test/CodeGen/ARM/swift-vldm.ll b/test/CodeGen/ARM/swift-vldm.ll index 67ae00a..9e50727 100644 --- a/test/CodeGen/ARM/swift-vldm.ll +++ b/test/CodeGen/ARM/swift-vldm.ll @@ -12,14 +12,14 @@ declare fastcc void @force_register(double %d0, double %d1, double %d2, double % define void @test_vldm(double* %x, double * %y) { entry: - %addr1 = getelementptr double * %x, i32 1 - %addr2 = getelementptr double * %x, i32 2 - %addr3 = getelementptr double * %x, i32 3 - %d0 = load double * %y - %d1 = load double * %x - %d2 = load double * %addr1 - %d3 = load double * %addr2 - %d4 = load double * %addr3 + %addr1 = getelementptr double, double * %x, i32 1 + %addr2 = getelementptr double, double * %x, i32 2 + %addr3 = getelementptr double, double * %x, i32 3 + %d0 = load double , double * %y + %d1 = load double , double * %x + %d2 = load double , double * %addr1 + %d3 = load double , double * %addr2 + %d4 = load double , double * %addr3 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we ; don't form a "vldmia rX, {d1, d2, d3, d4}". ; We are relying on the calling convention and that register allocation |