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author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
tree | c92f1907a6b8006628a4b01615f38264d29834ea /test/CodeGen/ARM/thumb1_return_sequence.ll | |
parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'test/CodeGen/ARM/thumb1_return_sequence.ll')
-rw-r--r-- | test/CodeGen/ARM/thumb1_return_sequence.ll | 48 |
1 files changed, 17 insertions, 31 deletions
diff --git a/test/CodeGen/ARM/thumb1_return_sequence.ll b/test/CodeGen/ARM/thumb1_return_sequence.ll index 318e6e4..c831260 100644 --- a/test/CodeGen/ARM/thumb1_return_sequence.ll +++ b/test/CodeGen/ARM/thumb1_return_sequence.ll @@ -3,7 +3,7 @@ ; CHECK-V4T-LABEL: clobberframe ; CHECK-V5T-LABEL: clobberframe -define <4 x i32> @clobberframe() #0 { +define <4 x i32> @clobberframe(<6 x i32>* %p) #0 { entry: ; Prologue ; -------- @@ -11,9 +11,10 @@ entry: ; CHECK-V4T: sub sp, ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %b = alloca <4 x i32>, align 16 + %b = alloca <6 x i32>, align 16 %a = alloca <4 x i32>, align 16 - store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16 + %stuff = load <6 x i32>* %p, align 16 + store <6 x i32> %stuff, <6 x i32>* %b, align 16 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16 %0 = load <4 x i32>* %a, align 16 ret <4 x i32> %0 @@ -70,40 +71,25 @@ entry: ; CHECK-V4T-LABEL: simpleframe ; CHECK-V5T-LABEL: simpleframe -define i32 @simpleframe() #0 { +define i32 @simpleframe(<6 x i32>* %p) #0 { entry: ; Prologue ; -------- ; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr} ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - %d = alloca i32, align 4 - store i32 1, i32* %a, align 4 - store i32 2, i32* %b, align 4 - store i32 3, i32* %c, align 4 - store i32 4, i32* %d, align 4 - %0 = load i32* %a, align 4 - %inc = add nsw i32 %0, 1 - store i32 %inc, i32* %a, align 4 - %1 = load i32* %b, align 4 - %inc1 = add nsw i32 %1, 1 - store i32 %inc1, i32* %b, align 4 - %2 = load i32* %c, align 4 - %inc2 = add nsw i32 %2, 1 - store i32 %inc2, i32* %c, align 4 - %3 = load i32* %d, align 4 - %inc3 = add nsw i32 %3, 1 - store i32 %inc3, i32* %d, align 4 - %4 = load i32* %a, align 4 - %5 = load i32* %b, align 4 - %add = add nsw i32 %4, %5 - %6 = load i32* %c, align 4 - %add4 = add nsw i32 %add, %6 - %7 = load i32* %d, align 4 - %add5 = add nsw i32 %add4, %7 + %0 = load <6 x i32>* %p, align 16 + %1 = extractelement <6 x i32> %0, i32 0 + %2 = extractelement <6 x i32> %0, i32 1 + %3 = extractelement <6 x i32> %0, i32 2 + %4 = extractelement <6 x i32> %0, i32 3 + %5 = extractelement <6 x i32> %0, i32 4 + %6 = extractelement <6 x i32> %0, i32 5 + %add1 = add nsw i32 %1, %2 + %add2 = add nsw i32 %add1, %3 + %add3 = add nsw i32 %add2, %4 + %add4 = add nsw i32 %add3, %5 + %add5 = add nsw i32 %add4, %6 ret i32 %add5 ; Epilogue |