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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/ARM/vcvt_combine.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/ARM/vcvt_combine.ll')
| -rw-r--r-- | test/CodeGen/ARM/vcvt_combine.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll index 07ba230..0c856e8 100644 --- a/test/CodeGen/ARM/vcvt_combine.ll +++ b/test/CodeGen/ARM/vcvt_combine.ll @@ -7,7 +7,7 @@ ; CHECK-NOT: vmul define void @t0() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> @@ -23,7 +23,7 @@ declare void @foo_int32x2_t(<2 x i32>) ; CHECK-NOT: vmul define void @t1() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> @@ -39,7 +39,7 @@ declare void @foo_uint32x2_t(<2 x i32>) ; CHECK: vmul define void @t2() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000> @@ -53,7 +53,7 @@ entry: ; CHECK: vmul define void @t3() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000> @@ -67,7 +67,7 @@ entry: ; CHECK-NOT: vmul define void @t4() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000> @@ -81,7 +81,7 @@ entry: ; CHECK-NOT: vmul define void @t5() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2 |