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author | Bob Wilson <bob.wilson@apple.com> | 2010-04-20 00:17:16 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2010-04-20 00:17:16 +0000 |
commit | 02170c00341a345cbc4bc6697e2b8d849b25724b (patch) | |
tree | 7e859bb5934b15bf3dc969256a17970b1622d5c4 /test/CodeGen/ARM/vld1.ll | |
parent | 6bcf52f00a4fc352e90ff11681a0e69f9757eb37 (diff) | |
download | external_llvm-02170c00341a345cbc4bc6697e2b8d849b25724b.zip external_llvm-02170c00341a345cbc4bc6697e2b8d849b25724b.tar.gz external_llvm-02170c00341a345cbc4bc6697e2b8d849b25724b.tar.bz2 |
Fix tests for Neon load/store intrinsics to match the i8* types expected by
the intrinsics. The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type. The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101840 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vld1.ll')
-rw-r--r-- | test/CodeGen/ARM/vld1.ll | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index f5383aa..c61ea8c 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -10,28 +10,32 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { define <4 x i16> @vld1i16(i16* %A) nounwind { ;CHECK: vld1i16: ;CHECK: vld1.16 - %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0) ret <4 x i16> %tmp1 } define <2 x i32> @vld1i32(i32* %A) nounwind { ;CHECK: vld1i32: ;CHECK: vld1.32 - %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0) ret <2 x i32> %tmp1 } define <2 x float> @vld1f(float* %A) nounwind { ;CHECK: vld1f: ;CHECK: vld1.32 - %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0) ret <2 x float> %tmp1 } define <1 x i64> @vld1i64(i64* %A) nounwind { ;CHECK: vld1i64: ;CHECK: vld1.64 - %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0) ret <1 x i64> %tmp1 } @@ -45,28 +49,32 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;CHECK: vld1Qi16: ;CHECK: vld1.16 - %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0) ret <8 x i16> %tmp1 } define <4 x i32> @vld1Qi32(i32* %A) nounwind { ;CHECK: vld1Qi32: ;CHECK: vld1.32 - %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0) ret <4 x i32> %tmp1 } define <4 x float> @vld1Qf(float* %A) nounwind { ;CHECK: vld1Qf: ;CHECK: vld1.32 - %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0) ret <4 x float> %tmp1 } define <2 x i64> @vld1Qi64(i64* %A) nounwind { ;CHECK: vld1Qi64: ;CHECK: vld1.64 - %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0) ret <2 x i64> %tmp1 } |