Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 13 insertions, 13 deletions

diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll
index 994f05d..444d0d5 100644
--- a/test/CodeGen/ARM/vld1.ll
+++ b/test/CodeGen/ARM/vld1.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vld1i8(i8* %A) nounwind {
-;CHECK: vld1i8:
+;CHECK-LABEL: vld1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld1.8 {d16}, [r0:64]
 	%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
@@ -10,7 +10,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld1i16(i16* %A) nounwind {
-;CHECK: vld1i16:
+;CHECK-LABEL: vld1i16:
 ;CHECK: vld1.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
@@ -19,7 +19,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
-;CHECK: vld1i16_update:
+;CHECK-LABEL: vld1i16_update:
 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -30,7 +30,7 @@ define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld1i32(i32* %A) nounwind {
-;CHECK: vld1i32:
+;CHECK-LABEL: vld1i32:
 ;CHECK: vld1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
@@ -39,7 +39,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
-;CHECK: vld1i32_update:
+;CHECK-LABEL: vld1i32_update:
 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -50,7 +50,7 @@ define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
 }
 
 define <2 x float> @vld1f(float* %A) nounwind {
-;CHECK: vld1f:
+;CHECK-LABEL: vld1f:
 ;CHECK: vld1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld1f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld1i64(i64* %A) nounwind {
-;CHECK: vld1i64:
+;CHECK-LABEL: vld1i64:
 ;CHECK: vld1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
@@ -66,7 +66,7 @@ define <1 x i64> @vld1i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
-;CHECK: vld1Qi8:
+;CHECK-LABEL: vld1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.8 {d16, d17}, [r0:64]
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -75,7 +75,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load.
 define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
-;CHECK: vld1Qi8_update:
+;CHECK-LABEL: vld1Qi8_update:
 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
 	%A = load i8** %ptr
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -85,7 +85,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
 }
 
 define <8 x i16> @vld1Qi16(i16* %A) nounwind {
-;CHECK: vld1Qi16:
+;CHECK-LABEL: vld1Qi16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -94,7 +94,7 @@ define <8 x i16> @vld1Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld1Qi32(i32* %A) nounwind {
-;CHECK: vld1Qi32:
+;CHECK-LABEL: vld1Qi32:
 ;CHECK: vld1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
@@ -102,7 +102,7 @@ define <4 x i32> @vld1Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld1Qf(float* %A) nounwind {
-;CHECK: vld1Qf:
+;CHECK-LABEL: vld1Qf:
 ;CHECK: vld1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
@@ -110,7 +110,7 @@ define <4 x float> @vld1Qf(float* %A) nounwind {
 }
 
 define <2 x i64> @vld1Qi64(i64* %A) nounwind {
-;CHECK: vld1Qi64:
+;CHECK-LABEL: vld1Qi64:
 ;CHECK: vld1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)