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author | Bob Wilson <bob.wilson@apple.com> | 2011-02-07 17:43:21 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2011-02-07 17:43:21 +0000 |
commit | 1c3ef90cab9a563427bdd3c2fcd875c717750562 (patch) | |
tree | 96e3030f27ad79d3147140f5ae0ecabf8f6b11c0 /test/CodeGen/ARM/vstlane.ll | |
parent | 7de6814405ab02591235f0826b8e6d98fd76c8ba (diff) | |
download | external_llvm-1c3ef90cab9a563427bdd3c2fcd875c717750562.zip external_llvm-1c3ef90cab9a563427bdd3c2fcd875c717750562.tar.gz external_llvm-1c3ef90cab9a563427bdd3c2fcd875c717750562.tar.bz2 |
Add codegen support for using post-increment NEON load/store instructions.
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vstlane.ll')
-rw-r--r-- | test/CodeGen/ARM/vstlane.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 9aa8d59..6cc052b 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -94,6 +94,19 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ret void } +;Check for a post-increment updating store with register increment. +define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { +;CHECK: vst2lanei16_update: +;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2 + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = load <4 x i16>* %B + call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2) + %tmp2 = getelementptr i16* %A, i32 %inc + store i16* %tmp2, i16** %ptr + ret void +} + define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2lanei32: ;CHECK: vst2.32 @@ -205,6 +218,19 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { +;CHECK: vst3laneQi32_update: +;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]! + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = load <4 x i32>* %B + call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) + %tmp2 = getelementptr i32* %A, i32 3 + store i32* %tmp2, i32** %ptr + ret void +} + define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3laneQf: ;CHECK: vst3.32 @@ -233,6 +259,18 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { +;CHECK: vst4lanei8_update: +;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! + %A = load i8** %ptr + %tmp1 = load <8 x i8>* %B + call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + %tmp2 = getelementptr i8* %A, i32 4 + store i8* %tmp2, i8** %ptr + ret void +} + define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4lanei16: ;CHECK: vst4.16 |