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| author | Evan Cheng <evan.cheng@apple.com> | 2012-03-06 23:33:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-03-06 23:33:32 +0000 |
| commit | 03be3622aae67aa095bc047bcac88cdebebaafd6 (patch) | |
| tree | 8e0bbac44c5e8e31ca5607430235028d76ffd120 /test/CodeGen/ARM | |
| parent | 4d0983a4d734280d481bb56472fe44ad0ddc447d (diff) | |
| download | external_llvm-03be3622aae67aa095bc047bcac88cdebebaafd6.zip external_llvm-03be3622aae67aa095bc047bcac88cdebebaafd6.tar.gz external_llvm-03be3622aae67aa095bc047bcac88cdebebaafd6.tar.bz2 | |
Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/shifter_operand.ll | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 521ffa1..eb971ff 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -54,12 +54,16 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A8: str [[REG]], [r0] +; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A8: str [[REG]], [r0, r1, lsl #2] +; A8-NOT: str [[REG]], [r0] ; A9: test4: -; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A9: str [[REG]], [r0] +; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A9: str [[REG]], [r0, r1, lsl #2] +; A9-NOT: str [[REG]], [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 |