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| author | Chad Rosier <mcrosier@apple.com> | 2012-02-08 02:29:21 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-02-08 02:29:21 +0000 |
| commit | 6fde8756215a725578b6afe678757f60d7f55d06 (patch) | |
| tree | caf747f4717d0d2850a54e3a9d9363442dada1cb /test/CodeGen/ARM | |
| parent | 99a7a13f4aa5bf8f272c95f7b09ba997d2b30a35 (diff) | |
| download | external_llvm-6fde8756215a725578b6afe678757f60d7f55d06.zip external_llvm-6fde8756215a725578b6afe678757f60d7f55d06.tar.gz external_llvm-6fde8756215a725578b6afe678757f60d7f55d06.tar.bz2 | |
[fast-isel] Add support for ORs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-binary.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel-binary.ll b/test/CodeGen/ARM/fast-isel-binary.ll index 06d9cd3..642fcd0 100644 --- a/test/CodeGen/ARM/fast-isel-binary.ll +++ b/test/CodeGen/ARM/fast-isel-binary.ll @@ -38,3 +38,39 @@ entry: store i16 %0, i16* %a.addr, align 4 ret void } + +define void @or_i1(i1 %a, i1 %b) nounwind ssp { +entry: +; ARM: or_i1 +; THUMB: or_i1 + %a.addr = alloca i1, align 4 + %0 = or i1 %a, %b +; ARM: orr r0, r0, r1 +; THUMB: orrs r0, r1 + store i1 %0, i1* %a.addr, align 4 + ret void +} + +define void @or_i8(i8 %a, i8 %b) nounwind ssp { +entry: +; ARM: or_i8 +; THUMB: or_i8 + %a.addr = alloca i8, align 4 + %0 = or i8 %a, %b +; ARM: orr r0, r0, r1 +; THUMB: orrs r0, r1 + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @or_i16(i16 %a, i16 %b) nounwind ssp { +entry: +; ARM: or_i16 +; THUMB: or_i16 + %a.addr = alloca i16, align 4 + %0 = or i16 %a, %b +; ARM: orr r0, r0, r1 +; THUMB: orrs r0, r1 + store i16 %0, i16* %a.addr, align 4 + ret void +} |