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| author | Edward O'Callaghan <eocallaghan@auroraux.org> | 2009-11-22 11:45:44 +0000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@auroraux.org> | 2009-11-22 11:45:44 +0000 |
| commit | 81fff07dafbbaec13216d9c1b520778042203728 (patch) | |
| tree | c4588c0cedc095913999fd9852e64410ce8460ff /test/CodeGen/ARM | |
| parent | 21870411d9c1807526b613d04c2ebae5a43c263b (diff) | |
| download | external_llvm-81fff07dafbbaec13216d9c1b520778042203728.zip external_llvm-81fff07dafbbaec13216d9c1b520778042203728.tar.gz external_llvm-81fff07dafbbaec13216d9c1b520778042203728.tar.bz2 | |
Convert a few tests to FileCheck for PR5307.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89584 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/bic.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fptoint.ll | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fsubs.ll | 9 | ||||
| -rw-r--r-- | test/CodeGen/ARM/mls.ll | 4 |
4 files changed, 18 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/bic.ll b/test/CodeGen/ARM/bic.ll index b16dcc6..5c6044d 100644 --- a/test/CodeGen/ARM/bic.ll +++ b/test/CodeGen/ARM/bic.ll @@ -6,8 +6,12 @@ define i32 @f1(i32 %a, i32 %b) { ret i32 %tmp1 } +; CHECK: bic r0, r0, r1 + define i32 @f2(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = and i32 %tmp, %a ret i32 %tmp1 } + +; CHECK: bic r0, r0, r1 diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll index 4cacc5d..f4906ff 100644 --- a/test/CodeGen/ARM/fptoint.ll +++ b/test/CodeGen/ARM/fptoint.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep -E {vmov\\W*r\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | not grep fmrrd +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s @i = weak global i32 0 ; <i32*> [#uses=2] @u = weak global i32 0 ; <i32*> [#uses=2] @@ -45,3 +44,7 @@ define void @foo9(double %x) { store i16 %tmp, i16* null ret void } + +; CHECK: vmov d0, r0, r1 +; CHECK-NOT: fmrrd + diff --git a/test/CodeGen/ARM/fsubs.ll b/test/CodeGen/ARM/fsubs.ll index f84ccdd..ae98be3 100644 --- a/test/CodeGen/ARM/fsubs.ll +++ b/test/CodeGen/ARM/fsubs.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vsub.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { entry: @@ -8,3 +8,6 @@ entry: ret float %0 } +; VFP2: vsub.f32 s0, s1, s0 +; NFP1: vsub.f32 d0, d1, d0 +; NFP0: vsub.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll index 85407fa..a6cdba4 100644 --- a/test/CodeGen/ARM/mls.ll +++ b/test/CodeGen/ARM/mls.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b @@ -12,3 +12,5 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) { %tmp2 = sub i32 %tmp1, %c ret i32 %tmp2 } + +; CHECK: mls r0, r0, r1, r2 |