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authorDuncan Sands <baldrick@free.fr>2012-04-07 20:04:00 +0000
committerDuncan Sands <baldrick@free.fr>2012-04-07 20:04:00 +0000
commit961d666be4f3714452ff9f15470f9255d85f0506 (patch)
tree3d1f81853d29f25e0f93ae99c3e7d85ded0d50f4 /test/CodeGen/ARM
parent5cd79bc14ca51019af4db735d13eac95dab088ed (diff)
downloadexternal_llvm-961d666be4f3714452ff9f15470f9255d85f0506.zip
external_llvm-961d666be4f3714452ff9f15470f9255d85f0506.tar.gz
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Convert floating point division by a constant into multiplication by the
reciprocal if converting to the reciprocal is exact. Do it even if inexact if -ffast-math. This substantially speeds up ac.f90 from the polyhedron benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154265 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r--test/CodeGen/ARM/vdiv_combine.ll12
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll
index 1387393..7fddbed 100644
--- a/test/CodeGen/ARM/vdiv_combine.ll
+++ b/test/CodeGen/ARM/vdiv_combine.ll
@@ -8,7 +8,7 @@ declare void @foo_int32x4_t(<4 x i32>)
; Test signed conversion.
; CHECK: t1
-; CHECK-NOT: vdiv
+; CHECK-NOT: {{vdiv|vmul}}
define void @t1() nounwind {
entry:
%tmp = load i32* @iin, align 4, !tbaa !3
@@ -24,7 +24,7 @@ declare void @foo_float32x2_t(<2 x float>)
; Test unsigned conversion.
; CHECK: t2
-; CHECK-NOT: vdiv
+; CHECK-NOT: {{vdiv|vmul}}
define void @t2() nounwind {
entry:
%tmp = load i32* @uin, align 4, !tbaa !3
@@ -38,7 +38,7 @@ entry:
; Test which should not fold due to non-power of 2.
; CHECK: t3
-; CHECK: vdiv
+; CHECK: {{vdiv|vmul}}
define void @t3() nounwind {
entry:
%tmp = load i32* @iin, align 4, !tbaa !3
@@ -52,7 +52,7 @@ entry:
; Test which should not fold due to power of 2 out of range.
; CHECK: t4
-; CHECK: vdiv
+; CHECK: {{vdiv|vmul}}
define void @t4() nounwind {
entry:
%tmp = load i32* @iin, align 4, !tbaa !3
@@ -66,7 +66,7 @@ entry:
; Test case where const is max power of 2 (i.e., 2^32).
; CHECK: t5
-; CHECK-NOT: vdiv
+; CHECK-NOT: {{vdiv|vmul}}
define void @t5() nounwind {
entry:
%tmp = load i32* @iin, align 4, !tbaa !3
@@ -80,7 +80,7 @@ entry:
; Test quadword.
; CHECK: t6
-; CHECK-NOT: vdiv
+; CHECK-NOT: {{vdiv|vmul}}
define void @t6() nounwind {
entry:
%tmp = load i32* @iin, align 4, !tbaa !3