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author | Evan Cheng <evan.cheng@apple.com> | 2010-10-21 01:12:00 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-21 01:12:00 +0000 |
commit | d6865de2d205d501e20d312ac66463be57dc44a1 (patch) | |
tree | 216394c7e7ce15318f375c076d41e8ecde0095a4 /test/CodeGen/ARM | |
parent | d7795540d0538fb79e70d0519858d463ac4375af (diff) | |
download | external_llvm-d6865de2d205d501e20d312ac66463be57dc44a1.zip external_llvm-d6865de2d205d501e20d312ac66463be57dc44a1.tar.gz external_llvm-d6865de2d205d501e20d312ac66463be57dc44a1.tar.bz2 |
Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r-- | test/CodeGen/ARM/fmscs.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/ARM/reg_sequence.ll | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index 103ce33..19359a1 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -19,6 +19,6 @@ entry: ; NFP0: vnmls.f32 s2, s1, s0 ; CORTEXA8: test: -; CORTEXA8: vnmls.f32 s2, s1, s0 +; CORTEXA8: vnmls.f32 s1, s2, s0 ; CORTEXA9: test: ; CORTEXA9: vnmls.f32 s0, s1, s2 diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 1a95897..3909554 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -75,7 +75,8 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ; CHECK: t3: ; CHECK: vld3.8 ; CHECK: vmul.i8 -; CHECK-NOT: vmov +; CHECK: vmov r +; CHECK-NOT: vmov d ; CHECK: vst3.8 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] |