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| author | Andrew Trick <atrick@apple.com> | 2013-05-25 03:08:10 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-05-25 03:08:10 +0000 |
| commit | dd0fb018a7cd2214c7bc5c6c767f626f99b47ba9 (patch) | |
| tree | 50fe35710d547f4df2e5f982e0a7c32791b3d680 /test/CodeGen/ARM | |
| parent | ac6d9bec671252dd1e596fa71180ff6b39d06b5d (diff) | |
| download | external_llvm-dd0fb018a7cd2214c7bc5c6c767f626f99b47ba9.zip external_llvm-dd0fb018a7cd2214c7bc5c6c767f626f99b47ba9.tar.gz external_llvm-dd0fb018a7cd2214c7bc5c6c767f626f99b47ba9.tar.bz2 | |
Track IR ordering of SelectionDAG nodes 3/4.
Remove the old IR ordering mechanism and switch to new one. Fix unit
test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/2011-08-25-ldmia_ret.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-pic.ll | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll index 216057a..91de08a 100644 --- a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll +++ b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll @@ -42,7 +42,7 @@ if.then: ; preds = %land.lhs.true ; If-convert the return ; CHECK: it ne ; Fold the CSR+return into a pop -; CHECK: popne {r4, r5, r7, pc} +; CHECK: pop {r4, r5, r6, r7, pc} sw.bb18: %call20 = tail call i32 @bar(i32 %in2) nounwind switch i32 %call20, label %sw.default56 [ diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll index 6bb9ea3..da7007b 100644 --- a/test/CodeGen/ARM/fast-isel-pic.ll +++ b/test/CodeGen/ARM/fast-isel-pic.ll @@ -15,7 +15,7 @@ entry: ; THUMB-ELF: LoadGV ; THUMB-ELF: ldr.n r[[reg0:[0-9]+]], ; THUMB-ELF: ldr.n r[[reg1:[0-9]+]], -; THUMB-ELF: ldr r[[reg0]], [r[[reg1]], r[[reg0]]] +; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]] ; ARM: LoadGV ; ARM: ldr [[reg1:r[0-9]+]], ; ARM: add [[reg1]], pc, [[reg1]] @@ -26,7 +26,7 @@ entry: ; ARMv7-ELF: LoadGV ; ARMv7-ELF: ldr r[[reg2:[0-9]+]], ; ARMv7-ELF: ldr r[[reg3:[0-9]+]], -; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] +; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]], r[[reg3]]] %tmp = load i32* @g ret i32 %tmp } @@ -43,7 +43,7 @@ entry: ; THUMB-ELF: LoadIndirectSymbol ; THUMB-ELF: ldr.n r[[reg3:[0-9]+]], ; THUMB-ELF: ldr.n r[[reg4:[0-9]+]], -; THUMB-ELF: ldr r[[reg3]], [r[[reg4]], r[[reg3]]] +; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]] ; ARM: LoadIndirectSymbol ; ARM: ldr [[reg4:r[0-9]+]], ; ARM: ldr [[reg4]], [pc, [[reg4]]] @@ -55,7 +55,7 @@ entry: ; ARMv7-ELF: LoadIndirectSymbol ; ARMv7-ELF: ldr r[[reg5:[0-9]+]], ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], -; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] +; ARMv7-ELF: ldr r[[reg5]], [r[[reg5]], r[[reg6]]] %tmp = load i32* @i ret i32 %tmp } |