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author | Scott Michel <scottm@aero.org> | 2009-01-26 03:31:40 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2009-01-26 03:31:40 +0000 |
commit | c9c8b2a804b2cd3d33a6a965e06a21ff93968f97 (patch) | |
tree | 6141f9f0ec12fefbdd984667613aaf33da6068af /test/CodeGen/CellSPU/fneg-fabs.ll | |
parent | 5bf4b7556f025587a8d1a14bd0fb39c12fc9c170 (diff) | |
download | external_llvm-c9c8b2a804b2cd3d33a6a965e06a21ff93968f97.zip external_llvm-c9c8b2a804b2cd3d33a6a965e06a21ff93968f97.tar.gz external_llvm-c9c8b2a804b2cd3d33a6a965e06a21ff93968f97.tar.bz2 |
CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
selection (SPUISelDAGtoDAG.cpp).
<rant>DAGCombiner will insert all kinds of 64-bit optimizations after
operation legalization occurs and now we have to do most of the work that
instruction selection should be doing twice (once to determine if v2i64
build_vector can be handled by SelectCode(), which then runs all of the
predicates a second time to select the necessary instructions.) But,
CellSPU is a good citizen.</rant>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/CellSPU/fneg-fabs.ll')
-rw-r--r-- | test/CodeGen/CellSPU/fneg-fabs.ll | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/test/CodeGen/CellSPU/fneg-fabs.ll b/test/CodeGen/CellSPU/fneg-fabs.ll index 70220a5..b6eca10 100644 --- a/test/CodeGen/CellSPU/fneg-fabs.ll +++ b/test/CodeGen/CellSPU/fneg-fabs.ll @@ -1,9 +1,10 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep fsmbi %t1.s | count 2 +; RUN: grep fsmbi %t1.s | count 3 ; RUN: grep 32768 %t1.s | count 2 ; RUN: grep xor %t1.s | count 4 -; RUN: grep and %t1.s | count 4 -; RUN: grep andbi %t1.s | count 2 +; RUN: grep and %t1.s | count 5 +; RUN: grep andbi %t1.s | count 3 + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -33,11 +34,11 @@ declare double @fabs(double) declare float @fabsf(float) define double @fabs_dp(double %X) { - %Y = call double @fabs( double %X ) ; <double> [#uses=1] + %Y = call double @fabs( double %X ) ret double %Y } define float @fabs_sp(float %X) { - %Y = call float @fabsf( float %X ) ; <float> [#uses=1] + %Y = call float @fabsf( float %X ) ret float %Y } |