Forward progress: crtbegin.c now compiles successfully!

Fixed CellSPU's A-form (local store) address mode, so that all globals,
externals, constant pool and jump table symbols are now wrapped within
a SPUISD::AFormAddr pseudo-instruction. This now identifies all local
store memory addresses, although it requires a bit of legerdemain during
instruction selection to properly select loads to and stores from local
store, properly generating "LQA" instructions.

Also added mul_ops.ll test harness for exercising integer multiplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46142 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 112 insertions, 11 deletions

diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll
index 27157ca..3c5810e 100644
--- a/test/CodeGen/CellSPU/call_indirect.ll
+++ b/test/CodeGen/CellSPU/call_indirect.ll
@@ -1,18 +1,18 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
-; RUN: grep bisl    %t1.s | count 6 &&
+; RUN: grep bisl    %t1.s | count 7 &&
 ; RUN: grep ila     %t1.s | count 1 &&
 ; RUN: grep rotqbyi %t1.s | count 4 &&
-; RUN: grep lqa     %t1.s | count 4 &&
+; RUN: grep lqa     %t1.s | count 5 &&
 ; RUN: grep lqd     %t1.s | count 6 &&
 ; RUN: grep dispatch_tab %t1.s | count 10
-; RUN: grep bisl    %t2.s | count 6 &&
-; RUN: grep ilhu    %t2.s | count 1 &&
-; RUN: grep iohl    %t2.s | count 1 &&
-; RUN: grep rotqby  %t2.s | count 5 &&
+; RUN: grep bisl    %t2.s | count 7 &&
+; RUN: grep ilhu    %t2.s | count 2 &&
+; RUN: grep iohl    %t2.s | count 2 &&
+; RUN: grep rotqby  %t2.s | count 6 &&
 ; RUN: grep lqd     %t2.s | count 12 &&
-; RUN: grep lqx     %t2.s | count 6 &&
-; RUN: grep il      %t2.s | count 7 &&
+; RUN: grep lqx     %t2.s | count 8 &&
+; RUN: grep il      %t2.s | count 9 &&
 ; RUN: grep ai      %t2.s | count 5 &&
 ; RUN: grep dispatch_tab %t2.s | count 7
 
@@ -38,3 +38,13 @@ entry:
 	tail call void %tmp2.5( i32 %i_arg, float %f_arg )
 	ret void
 }
+
+@ptr_list = internal global [1 x void ()*] [ void ()* inttoptr (i64 4294967295 to void ()*) ], align 4
+@ptr.a = internal global void ()** getelementptr ([1 x void ()*]* @ptr_list, i32 0, i32 1), align 16
+
+define void @double_indirect_call() {
+	%a = load void ()*** @ptr.a, align 16
+	%b = load void ()** %a, align 4
+	tail call void %b()
+	ret void
+}
diff --git a/test/CodeGen/CellSPU/mul_ops.ll b/test/CodeGen/CellSPU/mul_ops.ll
new file mode 100644
index 0000000..122e303
--- /dev/null
+++ b/test/CodeGen/CellSPU/mul_ops.ll
@@ -0,0 +1,90 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep mpy     %t1.s | count 44 &&
+; RUN: grep mpyu    %t1.s | count 4 &&
+; RUN: grep mpyh    %t1.s | count 10 &&
+; RUN: grep mpyhh   %t1.s | count 2 &&
+; RUN: grep rotma   %t1.s | count 12 &&
+; RUN: grep rotmahi %t1.s | count 4 &&
+; RUN: grep and     %t1.s | count 2 &&
+; RUN: grep selb    %t1.s | count 6 &&
+; RUN: grep fsmbi   %t1.s | count 4 &&
+; RUN: grep shli    %t1.s | count 4 &&
+; RUN: grep shlhi   %t1.s | count 4 &&
+; RUN: grep ila     %t1.s | count 2 &&
+; RUN: grep xsbh    %t1.s | count 8 &&
+; RUN: grep xshw    %t1.s | count 4
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; 32-bit multiply instruction generation:
+define <4 x i32> @mpy_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+entry:
+        %A = mul <4 x i32> %arg1, %arg2
+        ret <4 x i32> %A
+}
+
+define <4 x i32> @mpy_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+entry:
+        %A = mul <4 x i32> %arg2, %arg1
+        ret <4 x i32> %A
+}
+
+define <8 x i16> @mpy_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+entry:
+        %A = mul <8 x i16> %arg1, %arg2
+        ret <8 x i16> %A
+}
+
+define <8 x i16> @mpy_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+entry:
+        %A = mul <8 x i16> %arg2, %arg1
+        ret <8 x i16> %A
+}
+
+define <16 x i8> @mul_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+entry:
+        %A = mul <16 x i8> %arg2, %arg1
+        ret <16 x i8> %A
+}
+
+define <16 x i8> @mul_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+entry:
+        %A = mul <16 x i8> %arg1, %arg2
+        ret <16 x i8> %A
+}
+
+define i32 @mul_i32_1(i32 %arg1, i32 %arg2) {
+entry:
+	%A = mul i32 %arg2, %arg1
+	ret i32 %A
+}
+
+define i32 @mul_i32_2(i32 %arg1, i32 %arg2) {
+entry:
+	%A = mul i32 %arg1, %arg2
+	ret i32 %A
+}
+
+define i16 @mul_i16_1(i16 %arg1, i16 %arg2) {
+entry:
+	%A = mul i16 %arg2, %arg1
+	ret i16 %A
+}
+
+define i16 @mul_i16_2(i16 %arg1, i16 %arg2) {
+entry:
+	%A = mul i16 %arg1, %arg2
+	ret i16 %A
+}
+
+define i8 @mul_i8_1(i8 %arg1, i8 %arg2) {
+entry:
+	%A = mul i8 %arg2, %arg1
+	ret i8 %A
+}
+
+define i8 @mul_i8_2(i8 %arg1, i8 %arg2) {
+entry:
+	%A = mul i8 %arg1, %arg2
+	ret i8 %A
+}
diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll
index a28520c..b0286d1 100644
--- a/test/CodeGen/CellSPU/struct_1.ll
+++ b/test/CodeGen/CellSPU/struct_1.ll
@@ -16,9 +16,10 @@
 ; RUN: grep rotqbyi %t2.s | count 5 &&
 ; RUN: grep xshw    %t2.s | count 1 &&
 ; RUN: grep andi    %t2.s | count 4 &&
-; RUN: grep cbd     %t2.s | count 3 &&
-; RUN: grep chd     %t2.s | count 1 &&
-; RUN: grep cwd     %t2.s | count 3 &&
+; RUN: grep cbx     %t2.s | count 3 &&
+; RUN: grep chx     %t2.s | count 1 &&
+; RUN: grep cwx     %t2.s | count 1 &&
+; RUN: grep cwd     %t2.s | count 2 &&
 ; RUN: grep shufb   %t2.s | count 7 &&
 ; RUN: grep stqx    %t2.s | count 7