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authorSirish Pande <spande@codeaurora.org>2012-05-03 21:52:53 +0000
committerSirish Pande <spande@codeaurora.org>2012-05-03 21:52:53 +0000
commit26f61a158b3cce69252c05cc0e79f500d6c3d92e (patch)
treeb3324a781f77ce12e2e208bff093187bb293e00e /test/CodeGen/Hexagon/dualstore.ll
parentff9229ecf09c1909adafcdd58134d3ac1414b565 (diff)
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Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon/dualstore.ll')
-rw-r--r--test/CodeGen/Hexagon/dualstore.ll17
1 files changed, 17 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/dualstore.ll b/test/CodeGen/Hexagon/dualstore.ll
new file mode 100644
index 0000000..9b27dda
--- /dev/null
+++ b/test/CodeGen/Hexagon/dualstore.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; Check that we generate dual stores in one packet in V4
+
+; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}
+; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}
+; CHECK-NEXT: }
+
+@Reg = global i32 0, align 4
+define i32 @main() nounwind {
+entry:
+ %number= alloca i32, align 4
+ store i32 500000, i32* %number, align 4
+ %number1= alloca i32, align 4
+ store i32 100000, i32* %number1, align 4
+ ret i32 0
+}
+