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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 21:22:52 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2015-04-10 21:23:04 +0000 |
| commit | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Hexagon/extload-combine.ll | |
| parent | c75239e6119d0f9a74c57099d91cbc9bde56bf33 (diff) | |
| parent | 4c5e43da7792f75567b693105cc53e3f1992ad98 (diff) | |
| download | external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.zip external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.tar.gz external_llvm-31195f0bdca6ee2a5e72d07edf13e1d81206d949.tar.bz2 | |
Merge "Update aosp/master llvm for rebase to r233350"
Diffstat (limited to 'test/CodeGen/Hexagon/extload-combine.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/extload-combine.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll index b3b8bf0..519177f 100644 --- a/test/CodeGen/Hexagon/extload-combine.ll +++ b/test/CodeGen/Hexagon/extload-combine.ll @@ -19,7 +19,7 @@ define i64 @short_test1() #0 { ; CHECK: combine(#0, [[VAR]]) entry: store i16 0, i16* @a, align 2 - %0 = load i16* @b, align 2 + %0 = load i16, i16* @b, align 2 %conv2 = zext i16 %0 to i64 ret i64 %conv2 } @@ -30,7 +30,7 @@ define i64 @short_test2() #0 { ; CHECK: sxtw([[VAR1]]) entry: store i16 0, i16* @a, align 2 - %0 = load i16* @c, align 2 + %0 = load i16, i16* @c, align 2 %conv2 = sext i16 %0 to i64 ret i64 %conv2 } @@ -41,7 +41,7 @@ define i64 @char_test1() #0 { ; CHECK: combine(#0, [[VAR2]]) entry: store i8 0, i8* @char_a, align 1 - %0 = load i8* @char_b, align 1 + %0 = load i8, i8* @char_b, align 1 %conv2 = zext i8 %0 to i64 ret i64 %conv2 } @@ -52,7 +52,7 @@ define i64 @char_test2() #0 { ; CHECK: sxtw([[VAR3]]) entry: store i8 0, i8* @char_a, align 1 - %0 = load i8* @char_c, align 1 + %0 = load i8, i8* @char_c, align 1 %conv2 = sext i8 %0 to i64 ret i64 %conv2 } @@ -63,7 +63,7 @@ define i64 @int_test1() #0 { ; CHECK: combine(#0, [[VAR4]]) entry: store i32 0, i32* @int_a, align 4 - %0 = load i32* @int_b, align 4 + %0 = load i32, i32* @int_b, align 4 %conv = zext i32 %0 to i64 ret i64 %conv } @@ -74,7 +74,7 @@ define i64 @int_test2() #0 { ; CHECK: sxtw([[VAR5]]) entry: store i32 0, i32* @int_a, align 4 - %0 = load i32* @int_c, align 4 + %0 = load i32, i32* @int_c, align 4 %conv = sext i32 %0 to i64 ret i64 %conv } |