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authorPirama Arumuga Nainar <pirama@google.com>2015-04-10 22:08:18 +0000
committerAndroid Git Automerger <android-git-automerger@android.com>2015-04-10 22:08:18 +0000
commit13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch)
tree1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Hexagon/idxload-with-zero-offset.ll
parent0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff)
parent31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff)
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am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949': Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/Hexagon/idxload-with-zero-offset.ll')
-rw-r--r--test/CodeGen/Hexagon/idxload-with-zero-offset.ll24
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
index fbf1a3a..f1a9d38 100644
--- a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
+++ b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
@@ -7,8 +7,8 @@ define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
entry:
%tmp = add i32 %n, %m
- %scevgep9 = getelementptr i32* %a, i32 %tmp
- %val = load i32* %scevgep9, align 4
+ %scevgep9 = getelementptr i32, i32* %a, i32 %tmp
+ %val = load i32, i32* %scevgep9, align 4
ret i32 %val
}
@@ -18,8 +18,8 @@ define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
entry:
%tmp = add i32 %n, %m
- %scevgep9 = getelementptr i16* %a, i32 %tmp
- %val = load i16* %scevgep9, align 2
+ %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
+ %val = load i16, i16* %scevgep9, align 2
ret i16 %val
}
@@ -29,8 +29,8 @@ define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
entry:
%tmp = add i32 %n, %m
- %scevgep9 = getelementptr i16* %a, i32 %tmp
- %val = load i16* %scevgep9, align 2
+ %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
+ %val = load i16, i16* %scevgep9, align 2
%conv = sext i16 %val to i32
ret i32 %conv
}
@@ -41,8 +41,8 @@ define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
entry:
%tmp = add i32 %n, %m
- %scevgep9 = getelementptr i8* %a, i32 %tmp
- %val = load i8* %scevgep9, align 1
+ %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
+ %val = load i8, i8* %scevgep9, align 1
ret i8 %val
}
@@ -52,8 +52,8 @@ define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
entry:
%tmp = add i32 %n, %m
- %scevgep9 = getelementptr i8* %a, i32 %tmp
- %val = load i8* %scevgep9, align 1
+ %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
+ %val = load i8, i8* %scevgep9, align 1
%conv = sext i8 %val to i32
ret i32 %conv
}
@@ -64,7 +64,7 @@ define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
entry:
%tmp = add i32 %n, %m
- %scevgep9 = getelementptr i64* %a, i32 %tmp
- %val = load i64* %scevgep9, align 8
+ %scevgep9 = getelementptr i64, i64* %a, i32 %tmp
+ %val = load i64, i64* %scevgep9, align 8
ret i64 %val
}