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| author | Stephen Hines <srhines@google.com> | 2013-03-05 23:27:24 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2013-03-05 23:27:24 -0800 |
| commit | 5adb136be579e8fff3734461580cb34d1d2983b8 (patch) | |
| tree | bff1a422e9c9789df563aaf9a7e91e63e8ec0384 /test/CodeGen/Hexagon/validate-offset.ll | |
| parent | 227a4a4ade38716ba9eb3205f48b52910f3b955e (diff) | |
| parent | b3201c5cf1e183d840f7c99ff779d57f1549d8e5 (diff) | |
| download | external_llvm-5adb136be579e8fff3734461580cb34d1d2983b8.zip external_llvm-5adb136be579e8fff3734461580cb34d1d2983b8.tar.gz external_llvm-5adb136be579e8fff3734461580cb34d1d2983b8.tar.bz2 | |
Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226
Conflicts:
include/llvm/Support/ELF.h
lib/Support/DeltaAlgorithm.cpp
Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
Diffstat (limited to 'test/CodeGen/Hexagon/validate-offset.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/validate-offset.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/validate-offset.ll b/test/CodeGen/Hexagon/validate-offset.ll new file mode 100644 index 0000000..9e7d0aa --- /dev/null +++ b/test/CodeGen/Hexagon/validate-offset.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s -O0 + +; This is a regression test which makes sure that the offset check +; is available for STRiw_indexed instruction. This is required +; by 'Hexagon Expand Predicate Spill Code' pass. + +define i32 @f(i32 %a, i32 %b) nounwind { +entry: + %retval = alloca i32, align 4 + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + store i32 %b, i32* %b.addr, align 4 + %0 = load i32* %a.addr, align 4 + %1 = load i32* %b.addr, align 4 + %cmp = icmp sgt i32 %0, %1 + br i1 %cmp, label %if.then, label %if.else + +if.then: + %2 = load i32* %a.addr, align 4 + %3 = load i32* %b.addr, align 4 + %add = add nsw i32 %2, %3 + store i32 %add, i32* %retval + br label %return + +if.else: + %4 = load i32* %a.addr, align 4 + %5 = load i32* %b.addr, align 4 + %sub = sub nsw i32 %4, %5 + store i32 %sub, i32* %retval + br label %return + +return: + %6 = load i32* %retval + ret i32 %6 +} |