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author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-08 08:55:49 -0700 |
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committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-09 15:04:38 -0700 |
commit | 4c5e43da7792f75567b693105cc53e3f1992ad98 (patch) | |
tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Hexagon/vect/vect-shift-imm.ll | |
parent | c75239e6119d0f9a74c57099d91cbc9bde56bf33 (diff) | |
download | external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.zip external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.tar.gz external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.tar.bz2 |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
Diffstat (limited to 'test/CodeGen/Hexagon/vect/vect-shift-imm.ll')
-rw-r--r-- | test/CodeGen/Hexagon/vect/vect-shift-imm.ll | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/vect/vect-shift-imm.ll b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll new file mode 100644 index 0000000..4861181 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH +; +; Make sure that the instructions with immediate operands are generated. +; CHECK-ASLW: vaslw({{.*}}, #9) +; CHECK-ASRW: vasrw({{.*}}, #8) +; CHECK-LSRW: vlsrw({{.*}}, #7) +; CHECK-ASLH: vaslh({{.*}}, #6) +; CHECK-ASRH: vasrh({{.*}}, #5) +; CHECK-LSRH: vlsrh({{.*}}, #4) + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define i64 @foo(i64 %x) nounwind readnone { +entry: + %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9) + %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8) + %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7) + %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6) + %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5) + %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4) + %add = add i64 %1, %0 + %add1 = add i64 %add, %2 + %add2 = add i64 %add1, %3 + %add3 = add i64 %add2, %4 + %add4 = add i64 %add3, %5 + ret i64 %add4 +} + +declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone + |