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author | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-06 11:46:36 -0700 |
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committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-18 10:52:30 -0700 |
commit | 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 (patch) | |
tree | c0104029af14e9f47c2ef58ca60e6137691f3c9b /test/CodeGen/Hexagon | |
parent | e1bc145815f4334641be19f1c45ecf85d25b6e5a (diff) | |
download | external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.zip external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.gz external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.bz2 |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
Diffstat (limited to 'test/CodeGen/Hexagon')
-rw-r--r-- | test/CodeGen/Hexagon/adde.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/expand-condsets-basic.ll | 11 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/expand-condsets-rm-segment.ll | 131 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/expand-condsets-undef.ll | 28 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/i16_VarArg.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/i1_VarArg.ll | 12 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/i8_VarArg.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/sube.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll | 31 |
9 files changed, 211 insertions, 10 deletions
diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll index 6d060c1..5a8345c 100644 --- a/test/CodeGen/Hexagon/adde.ll +++ b/test/CodeGen/Hexagon/adde.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s ; CHECK: r{{[0-9]+:[0-9]+}} = #0 ; CHECK: r{{[0-9]+:[0-9]+}} = #1 diff --git a/test/CodeGen/Hexagon/expand-condsets-basic.ll b/test/CodeGen/Hexagon/expand-condsets-basic.ll new file mode 100644 index 0000000..16fe8af --- /dev/null +++ b/test/CodeGen/Hexagon/expand-condsets-basic.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: if{{.*}}add +; CHECK: if{{.*}}sub + +define i32 @foo (i1 %a, i32 %b, i32 %c, i32 %d) nounwind { + %1 = add i32 %b, %d + %2 = sub i32 %c, %d + %3 = select i1 %a, i32 %1, i32 %2 + ret i32 %3 +} + diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll b/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll new file mode 100644 index 0000000..cde7e6a --- /dev/null +++ b/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll @@ -0,0 +1,131 @@ +; RUN: llc -O2 < %s +; REQUIRES: asserts + +target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" +target triple = "hexagon-unknown--elf" + +%struct.cpumask = type { [1 x i32] } +%struct.load_weight = type { i32, i32 } + +@sysctl_sched_latency = global i32 6000000, align 4 +@normalized_sysctl_sched_latency = global i32 6000000, align 4 +@sysctl_sched_tunable_scaling = global i8 1, align 1 +@sysctl_sched_min_granularity = global i32 750000, align 4 +@normalized_sysctl_sched_min_granularity = global i32 750000, align 4 +@sysctl_sched_wakeup_granularity = global i32 1000000, align 4 +@normalized_sysctl_sched_wakeup_granularity = global i32 1000000, align 4 +@sysctl_sched_migration_cost = constant i32 500000, align 4 +@sysctl_sched_shares_window = global i32 10000000, align 4 +@sysctl_sched_child_runs_first = common global i32 0, align 4 +@cpu_online_mask = external constant %struct.cpumask* + +; Function Attrs: noinline nounwind +define void @sched_init_granularity() #0 { +entry: + tail call fastcc void @update_sysctl() + ret void +} + +; Function Attrs: noinline nounwind +define internal fastcc void @update_sysctl() #0 { +entry: + %call = tail call i32 @get_update_sysctl_factor() + %0 = load i32, i32* @normalized_sysctl_sched_min_granularity, align 4, !tbaa !1 + %mul = mul i32 %0, %call + store i32 %mul, i32* @sysctl_sched_min_granularity, align 4, !tbaa !1 + %1 = load i32, i32* @normalized_sysctl_sched_latency, align 4, !tbaa !1 + %mul1 = mul i32 %1, %call + store i32 %mul1, i32* @sysctl_sched_latency, align 4, !tbaa !1 + %2 = load i32, i32* @normalized_sysctl_sched_wakeup_granularity, align 4, !tbaa !1 + %mul2 = mul i32 %2, %call + store i32 %mul2, i32* @sysctl_sched_wakeup_granularity, align 4, !tbaa !1 + ret void +} + +; Function Attrs: noinline nounwind +define i32 @calc_delta_mine(i32 %delta_exec, i32 %weight, %struct.load_weight* nocapture %lw) #0 { +entry: + %cmp = icmp ugt i32 %weight, 1 + %conv = zext i32 %delta_exec to i64 + br i1 %cmp, label %if.then, label %if.end, !prof !5 + +if.then: ; preds = %entry + %conv2 = zext i32 %weight to i64 + %mul = mul i64 %conv2, %conv + br label %if.end + +if.end: ; preds = %entry, %if.then + %tmp.0 = phi i64 [ %mul, %if.then ], [ %conv, %entry ] + %inv_weight = getelementptr inbounds %struct.load_weight, %struct.load_weight* %lw, i32 0, i32 1 + %0 = load i32, i32* %inv_weight, align 4, !tbaa !6 + %tobool4 = icmp eq i32 %0, 0 + br i1 %tobool4, label %if.then5, label %if.end22 + +if.then5: ; preds = %if.end + %weight7 = getelementptr inbounds %struct.load_weight, %struct.load_weight* %lw, i32 0, i32 0 + %1 = load i32, i32* %weight7, align 4, !tbaa !9 + %lnot9 = icmp eq i32 %1, 0 + br i1 %lnot9, label %if.then17, label %if.else19, !prof !10 + +if.then17: ; preds = %if.then5 + store i32 -1, i32* %inv_weight, align 4, !tbaa !6 + br label %if.end22 + +if.else19: ; preds = %if.then5 + %div = udiv i32 -1, %1 + store i32 %div, i32* %inv_weight, align 4, !tbaa !6 + br label %if.end22 + +if.end22: ; preds = %if.end, %if.then17, %if.else19 + %2 = phi i32 [ %0, %if.end ], [ -1, %if.then17 ], [ %div, %if.else19 ] + %cmp23 = icmp ugt i64 %tmp.0, 4294967295 + br i1 %cmp23, label %if.then31, label %if.else37, !prof !10 + +if.then31: ; preds = %if.end22 + %add = add i64 %tmp.0, 32768 + %shr = lshr i64 %add, 16 + %conv33 = zext i32 %2 to i64 + %mul34 = mul i64 %conv33, %shr + %add35 = add i64 %mul34, 32768 + %shr36 = lshr i64 %add35, 16 + br label %if.end43 + +if.else37: ; preds = %if.end22 + %conv39 = zext i32 %2 to i64 + %mul40 = mul i64 %conv39, %tmp.0 + %add41 = add i64 %mul40, 2147483648 + %shr42 = lshr i64 %add41, 32 + br label %if.end43 + +if.end43: ; preds = %if.else37, %if.then31 + %tmp.1 = phi i64 [ %shr36, %if.then31 ], [ %shr42, %if.else37 ] + %cmp49 = icmp ult i64 %tmp.1, 2147483647 + %3 = trunc i64 %tmp.1 to i32 + %conv51 = select i1 %cmp49, i32 %3, i32 2147483647 + ret i32 %conv51 +} + +declare i32 @get_update_sysctl_factor() #0 +declare i32 @__bitmap_weight(i32*, i32) #1 + +attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } + +!llvm.ident = !{!0} + +!0 = !{!"Clang 3.1"} +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{!"branch_weights", i32 64, i32 4} +!6 = !{!7, !8, i64 4} +!7 = !{!"load_weight", !8, i64 0, !8, i64 4} +!8 = !{!"long", !3, i64 0} +!9 = !{!7, !8, i64 0} +!10 = !{!"branch_weights", i32 4, i32 64} +!11 = !{!12, !12, i64 0} +!12 = !{!"any pointer", !3, i64 0} +!13 = !{!3, !3, i64 0} +!14 = !{i32 45854, i32 45878} diff --git a/test/CodeGen/Hexagon/expand-condsets-undef.ll b/test/CodeGen/Hexagon/expand-condsets-undef.ll new file mode 100644 index 0000000..85e72aa --- /dev/null +++ b/test/CodeGen/Hexagon/expand-condsets-undef.ll @@ -0,0 +1,28 @@ +; RUN: llc -O2 < %s +; REQUIRES: asserts + +target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32" +target triple = "hexagon" + +; Function Attrs: nounwind optsize ssp +define internal fastcc void @foo() nounwind { +if.else473: + %0 = load i64, i64* undef, align 8 + %sub = sub nsw i64 undef, %0 + %conv476 = sitofp i64 %sub to double + %mul477 = fmul double %conv476, 0x3F50624DE0000000 + br i1 undef, label %cond.true540, label %cond.end548 + +cond.true540: + %1 = fptrunc double %mul477 to float + %2 = fptosi float %1 to i32 + br label %cond.end548 + +cond.end548: + %cond549 = phi i32 [ %2, %cond.true540 ], [ undef, %if.else473 ] + call void @bar(i32 %cond549) nounwind + unreachable +} + +declare void @bar(i32) nounwind + diff --git a/test/CodeGen/Hexagon/i16_VarArg.ll b/test/CodeGen/Hexagon/i16_VarArg.ll index 41cecec..ba98f62 100644 --- a/test/CodeGen/Hexagon/i16_VarArg.ll +++ b/test/CodeGen/Hexagon/i16_VarArg.ll @@ -35,6 +35,6 @@ define i32 @main() { %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0 %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0 %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0 - call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 ) + call i32 (i8*, ...) @printf( i8* %lt_s, i16 %val1 ) ret i32 0 } diff --git a/test/CodeGen/Hexagon/i1_VarArg.ll b/test/CodeGen/Hexagon/i1_VarArg.ll index 8b5625c..1908b3c 100644 --- a/test/CodeGen/Hexagon/i1_VarArg.ll +++ b/test/CodeGen/Hexagon/i1_VarArg.ll @@ -34,11 +34,11 @@ define i32 @main() { %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0 %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0 %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0 - call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r ) - call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r ) - call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r ) - call i32 (i8*, ...)* @printf( i8* %ge_s, i1 %ge_r ) - call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r ) - call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r ) + call i32 (i8*, ...) @printf( i8* %lt_s, i1 %lt_r ) + call i32 (i8*, ...) @printf( i8* %le_s, i1 %le_r ) + call i32 (i8*, ...) @printf( i8* %gt_s, i1 %gt_r ) + call i32 (i8*, ...) @printf( i8* %ge_s, i1 %ge_r ) + call i32 (i8*, ...) @printf( i8* %eq_s, i1 %eq_r ) + call i32 (i8*, ...) @printf( i8* %ne_s, i1 %ne_r ) ret i32 0 } diff --git a/test/CodeGen/Hexagon/i8_VarArg.ll b/test/CodeGen/Hexagon/i8_VarArg.ll index 7283ba4..c40a6a9 100644 --- a/test/CodeGen/Hexagon/i8_VarArg.ll +++ b/test/CodeGen/Hexagon/i8_VarArg.ll @@ -35,6 +35,6 @@ define i32 @main() { %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0 %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0 %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0 - call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 ) + call i32 (i8*, ...) @printf( i8* %lt_s, i8 %val1 ) ret i32 0 } diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll index 735ac9e..1a78822 100644 --- a/test/CodeGen/Hexagon/sube.ll +++ b/test/CodeGen/Hexagon/sube.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s ; CHECK: r{{[0-9]+:[0-9]+}} = #0 ; CHECK: r{{[0-9]+:[0-9]+}} = #1 diff --git a/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll b/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll new file mode 100644 index 0000000..90fb75e --- /dev/null +++ b/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; CHECK-LABEL: tail_memcpy: +; CHECK: jump memcpy +define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false) + ret void +} + +; CHECK-LABEL: tail_memmove: +; CHECK: jump memmove +define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 { +entry: + tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false) + ret void +} + +; CHECK-LABEL: tail_memset: +; CHECK: jump memset +define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 { +entry: + tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0 + +attributes #0 = { nounwind } |