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author | Manman Ren <manman.ren@gmail.com> | 2013-08-21 22:20:53 +0000 |
---|---|---|
committer | Manman Ren <manman.ren@gmail.com> | 2013-08-21 22:20:53 +0000 |
commit | bf9d6e5c3743e873164765cbe38cc1bd10ee18ab (patch) | |
tree | c3f45b5fa047527d7c10bbb4b418a8ad0a5940ed /test/CodeGen/Hexagon | |
parent | 23dcb187fb2a195ad7dbc35d3cee2c33edb7bfc3 (diff) | |
download | external_llvm-bf9d6e5c3743e873164765cbe38cc1bd10ee18ab.zip external_llvm-bf9d6e5c3743e873164765cbe38cc1bd10ee18ab.tar.gz external_llvm-bf9d6e5c3743e873164765cbe38cc1bd10ee18ab.tar.bz2 |
TBAA: remove !tbaa from testing cases when they are not needed.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188944 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
-rw-r--r-- | test/CodeGen/Hexagon/combine_ir.ll | 15 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/memops.ll | 509 |
2 files changed, 257 insertions, 267 deletions
diff --git a/test/CodeGen/Hexagon/combine_ir.ll b/test/CodeGen/Hexagon/combine_ir.ll index 8b99ef7..e100cf7 100644 --- a/test/CodeGen/Hexagon/combine_ir.ll +++ b/test/CodeGen/Hexagon/combine_ir.ll @@ -4,7 +4,7 @@ define void @word(i32* nocapture %a) nounwind { entry: - %0 = load i32* %a, align 4, !tbaa !0 + %0 = load i32* %a, align 4 %1 = zext i32 %0 to i64 tail call void @bar(i64 %1) nounwind ret void @@ -17,10 +17,10 @@ declare void @bar(i64) define void @halfword(i16* nocapture %a) nounwind { entry: - %0 = load i16* %a, align 2, !tbaa !3 + %0 = load i16* %a, align 2 %1 = zext i16 %0 to i64 %add.ptr = getelementptr inbounds i16* %a, i32 1 - %2 = load i16* %add.ptr, align 2, !tbaa !3 + %2 = load i16* %add.ptr, align 2 %3 = zext i16 %2 to i64 %4 = shl nuw nsw i64 %3, 16 %ins = or i64 %4, %1 @@ -33,18 +33,13 @@ entry: define void @byte(i8* nocapture %a) nounwind { entry: - %0 = load i8* %a, align 1, !tbaa !1 + %0 = load i8* %a, align 1 %1 = zext i8 %0 to i64 %add.ptr = getelementptr inbounds i8* %a, i32 1 - %2 = load i8* %add.ptr, align 1, !tbaa !1 + %2 = load i8* %add.ptr, align 1 %3 = zext i8 %2 to i64 %4 = shl nuw nsw i64 %3, 8 %ins = or i64 %4, %1 tail call void @bar(i64 %ins) nounwind ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"short", metadata !1} diff --git a/test/CodeGen/Hexagon/memops.ll b/test/CodeGen/Hexagon/memops.ll index 5498848..fca1a73 100644 --- a/test/CodeGen/Hexagon/memops.ll +++ b/test/CodeGen/Hexagon/memops.ll @@ -4,11 +4,11 @@ define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i8 - store i8 %conv1, i8* %p, align 1, !tbaa !0 + store i8 %conv1, i8* %p, align 1 ret void } @@ -16,11 +16,11 @@ define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv1 = zext i8 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i8 - store i8 %conv2, i8* %p, align 1, !tbaa !0 + store i8 %conv2, i8* %p, align 1 ret void } @@ -28,51 +28,51 @@ define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv1 = zext i8 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %p, align 1, !tbaa !0 + store i8 %conv2, i8* %p, align 1 ret void } define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %or3 = or i8 %0, %x - store i8 %or3, i8* %p, align 1, !tbaa !0 + store i8 %or3, i8* %p, align 1 ret void } define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %and3 = and i8 %0, %x - store i8 %and3, i8* %p, align 1, !tbaa !0 + store i8 %and3, i8* %p, align 1 ret void } define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 %conv1 = trunc i32 %and to i8 - store i8 %conv1, i8* %p, align 1, !tbaa !0 + store i8 %conv1, i8* %p, align 1 ret void } define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i8 - store i8 %conv1, i8* %p, align 1, !tbaa !0 + store i8 %conv1, i8* %p, align 1 ret void } @@ -80,11 +80,11 @@ define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -93,11 +93,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -106,11 +106,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -118,9 +118,9 @@ define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext % entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %or3 = or i8 %0, %x - store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %or3, i8* %add.ptr, align 1 ret void } @@ -128,9 +128,9 @@ define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %and3 = and i8 %0, %x - store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %and3, i8* %add.ptr, align 1 ret void } @@ -138,11 +138,11 @@ define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 %conv1 = trunc i32 %and to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -150,11 +150,11 @@ define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -162,11 +162,11 @@ define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -175,11 +175,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -188,11 +188,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -200,9 +200,9 @@ define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) noun entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %or3 = or i8 %0, %x - store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %or3, i8* %add.ptr, align 1 ret void } @@ -210,9 +210,9 @@ define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nou entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %and3 = and i8 %0, %x - store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %and3, i8* %add.ptr, align 1 ret void } @@ -220,11 +220,11 @@ define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 %conv1 = trunc i32 %and to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -232,22 +232,22 @@ define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } define void @memop_signed_char_add5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i8 - store i8 %conv1, i8* %p, align 1, !tbaa !0 + store i8 %conv1, i8* %p, align 1 ret void } @@ -255,11 +255,11 @@ define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv13 = zext i8 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i8 - store i8 %conv2, i8* %p, align 1, !tbaa !0 + store i8 %conv2, i8* %p, align 1 ret void } @@ -267,51 +267,51 @@ define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv13 = zext i8 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %p, align 1, !tbaa !0 + store i8 %conv2, i8* %p, align 1 ret void } define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %or3 = or i8 %0, %x - store i8 %or3, i8* %p, align 1, !tbaa !0 + store i8 %or3, i8* %p, align 1 ret void } define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %and3 = and i8 %0, %x - store i8 %and3, i8* %p, align 1, !tbaa !0 + store i8 %and3, i8* %p, align 1 ret void } define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 %conv1 = trunc i32 %and to i8 - store i8 %conv1, i8* %p, align 1, !tbaa !0 + store i8 %conv1, i8* %p, align 1 ret void } define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i8* %p, align 1, !tbaa !0 + %0 = load i8* %p, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i8 - store i8 %conv1, i8* %p, align 1, !tbaa !0 + store i8 %conv1, i8* %p, align 1 ret void } @@ -319,11 +319,11 @@ define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -332,11 +332,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -345,11 +345,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -357,9 +357,9 @@ define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %or3 = or i8 %0, %x - store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %or3, i8* %add.ptr, align 1 ret void } @@ -367,9 +367,9 @@ define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %and3 = and i8 %0, %x - store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %and3, i8* %add.ptr, align 1 ret void } @@ -377,11 +377,11 @@ define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 %conv1 = trunc i32 %and to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -389,11 +389,11 @@ define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -401,11 +401,11 @@ define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -414,11 +414,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -427,11 +427,11 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr, align 1 ret void } @@ -439,9 +439,9 @@ define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwi entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %or3 = or i8 %0, %x - store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %or3, i8* %add.ptr, align 1 ret void } @@ -449,9 +449,9 @@ define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounw entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %and3 = and i8 %0, %x - store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + store i8 %and3, i8* %add.ptr, align 1 ret void } @@ -459,11 +459,11 @@ define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 %conv1 = trunc i32 %and to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -471,22 +471,22 @@ define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i16 - store i16 %conv1, i16* %p, align 2, !tbaa !2 + store i16 %conv1, i16* %p, align 2 ret void } @@ -494,11 +494,11 @@ define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwin entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv1 = zext i16 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i16 - store i16 %conv2, i16* %p, align 2, !tbaa !2 + store i16 %conv2, i16* %p, align 2 ret void } @@ -506,51 +506,51 @@ define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwin entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv1 = zext i16 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %p, align 2, !tbaa !2 + store i16 %conv2, i16* %p, align 2 ret void } define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %or3 = or i16 %0, %x - store i16 %or3, i16* %p, align 2, !tbaa !2 + store i16 %or3, i16* %p, align 2 ret void } define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %and3 = and i16 %0, %x - store i16 %and3, i16* %p, align 2, !tbaa !2 + store i16 %and3, i16* %p, align 2 ret void } define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 %conv1 = trunc i32 %and to i16 - store i16 %conv1, i16* %p, align 2, !tbaa !2 + store i16 %conv1, i16* %p, align 2 ret void } define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i16 - store i16 %conv1, i16* %p, align 2, !tbaa !2 + store i16 %conv1, i16* %p, align 2 ret void } @@ -558,11 +558,11 @@ define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -571,11 +571,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -584,11 +584,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -596,9 +596,9 @@ define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroex entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %or3 = or i16 %0, %x - store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %or3, i16* %add.ptr, align 2 ret void } @@ -606,9 +606,9 @@ define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroe entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %and3 = and i16 %0, %x - store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %and3, i16* %add.ptr, align 2 ret void } @@ -616,11 +616,11 @@ define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwi entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 %conv1 = trunc i32 %and to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -628,11 +628,11 @@ define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwi entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -640,11 +640,11 @@ define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -653,11 +653,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -666,11 +666,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -678,9 +678,9 @@ define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) n entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %or3 = or i16 %0, %x - store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %or3, i16* %add.ptr, align 2 ret void } @@ -688,9 +688,9 @@ define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %and3 = and i16 %0, %x - store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %and3, i16* %add.ptr, align 2 ret void } @@ -698,11 +698,11 @@ define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 %conv1 = trunc i32 %and to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -710,22 +710,22 @@ define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } define void @memop_signed_short_add5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i16 - store i16 %conv1, i16* %p, align 2, !tbaa !2 + store i16 %conv1, i16* %p, align 2 ret void } @@ -733,11 +733,11 @@ define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv13 = zext i16 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i16 - store i16 %conv2, i16* %p, align 2, !tbaa !2 + store i16 %conv2, i16* %p, align 2 ret void } @@ -745,51 +745,51 @@ define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv13 = zext i16 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %p, align 2, !tbaa !2 + store i16 %conv2, i16* %p, align 2 ret void } define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %or3 = or i16 %0, %x - store i16 %or3, i16* %p, align 2, !tbaa !2 + store i16 %or3, i16* %p, align 2 ret void } define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %and3 = and i16 %0, %x - store i16 %and3, i16* %p, align 2, !tbaa !2 + store i16 %and3, i16* %p, align 2 ret void } define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 %conv1 = trunc i32 %and to i16 - store i16 %conv1, i16* %p, align 2, !tbaa !2 + store i16 %conv1, i16* %p, align 2 ret void } define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i16* %p, align 2, !tbaa !2 + %0 = load i16* %p, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i16 - store i16 %conv1, i16* %p, align 2, !tbaa !2 + store i16 %conv1, i16* %p, align 2 ret void } @@ -797,11 +797,11 @@ define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -810,11 +810,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -823,11 +823,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -835,9 +835,9 @@ define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %or3 = or i16 %0, %x - store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %or3, i16* %add.ptr, align 2 ret void } @@ -845,9 +845,9 @@ define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %and3 = and i16 %0, %x - store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %and3, i16* %add.ptr, align 2 ret void } @@ -855,11 +855,11 @@ define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 %conv1 = trunc i32 %and to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -867,11 +867,11 @@ define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -879,11 +879,11 @@ define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -892,11 +892,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -905,11 +905,11 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv2, i16* %add.ptr, align 2 ret void } @@ -917,9 +917,9 @@ define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nou entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %or3 = or i16 %0, %x - store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %or3, i16* %add.ptr, align 2 ret void } @@ -927,9 +927,9 @@ define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) no entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %and3 = and i16 %0, %x - store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + store i16 %and3, i16* %add.ptr, align 2 ret void } @@ -937,11 +937,11 @@ define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 %conv1 = trunc i32 %and to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -949,74 +949,74 @@ define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2, !tbaa !2 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + store i16 %conv1, i16* %add.ptr, align 2 ret void } define void @memop_signed_int_add5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %add = add i32 %0, 5 - store i32 %add, i32* %p, align 4, !tbaa !3 + store i32 %add, i32* %p, align 4 ret void } define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %add = add i32 %0, %x - store i32 %add, i32* %p, align 4, !tbaa !3 + store i32 %add, i32* %p, align 4 ret void } define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %sub = sub i32 %0, %x - store i32 %sub, i32* %p, align 4, !tbaa !3 + store i32 %sub, i32* %p, align 4 ret void } define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %or = or i32 %0, %x - store i32 %or, i32* %p, align 4, !tbaa !3 + store i32 %or, i32* %p, align 4 ret void } define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %and = and i32 %0, %x - store i32 %and, i32* %p, align 4, !tbaa !3 + store i32 %and, i32* %p, align 4 ret void } define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %and = and i32 %0, -33 - store i32 %and, i32* %p, align 4, !tbaa !3 + store i32 %and, i32* %p, align 4 ret void } define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %or = or i32 %0, 128 - store i32 %or, i32* %p, align 4, !tbaa !3 + store i32 %or, i32* %p, align 4 ret void } @@ -1024,9 +1024,9 @@ define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add i32 %0, 5 - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1034,9 +1034,9 @@ define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounw entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add i32 %0, %x - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1044,9 +1044,9 @@ define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounw entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %sub = sub i32 %0, %x - store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + store i32 %sub, i32* %add.ptr, align 4 ret void } @@ -1054,9 +1054,9 @@ define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwi entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, %x - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } @@ -1064,9 +1064,9 @@ define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounw entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, %x - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1074,9 +1074,9 @@ define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, -33 - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1084,9 +1084,9 @@ define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, 128 - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } @@ -1094,9 +1094,9 @@ define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add i32 %0, 5 - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1104,9 +1104,9 @@ define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add i32 %0, %x - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1114,9 +1114,9 @@ define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %sub = sub i32 %0, %x - store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + store i32 %sub, i32* %add.ptr, align 4 ret void } @@ -1124,9 +1124,9 @@ define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, %x - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } @@ -1134,9 +1134,9 @@ define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, %x - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1144,9 +1144,9 @@ define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, -33 - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1154,72 +1154,72 @@ define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, 128 - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %add = add nsw i32 %0, 5 - store i32 %add, i32* %p, align 4, !tbaa !3 + store i32 %add, i32* %p, align 4 ret void } define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %add = add nsw i32 %0, %x - store i32 %add, i32* %p, align 4, !tbaa !3 + store i32 %add, i32* %p, align 4 ret void } define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %sub = sub nsw i32 %0, %x - store i32 %sub, i32* %p, align 4, !tbaa !3 + store i32 %sub, i32* %p, align 4 ret void } define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %or = or i32 %0, %x - store i32 %or, i32* %p, align 4, !tbaa !3 + store i32 %or, i32* %p, align 4 ret void } define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %and = and i32 %0, %x - store i32 %and, i32* %p, align 4, !tbaa !3 + store i32 %and, i32* %p, align 4 ret void } define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %and = and i32 %0, -33 - store i32 %and, i32* %p, align 4, !tbaa !3 + store i32 %and, i32* %p, align 4 ret void } define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i32* %p, align 4, !tbaa !3 + %0 = load i32* %p, align 4 %or = or i32 %0, 128 - store i32 %or, i32* %p, align 4, !tbaa !3 + store i32 %or, i32* %p, align 4 ret void } @@ -1227,9 +1227,9 @@ define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add nsw i32 %0, 5 - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1237,9 +1237,9 @@ define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nou entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add nsw i32 %0, %x - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1247,9 +1247,9 @@ define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nou entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %sub = sub nsw i32 %0, %x - store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + store i32 %sub, i32* %add.ptr, align 4 ret void } @@ -1257,9 +1257,9 @@ define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) noun entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, %x - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } @@ -1267,9 +1267,9 @@ define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nou entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, %x - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1277,9 +1277,9 @@ define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, -33 - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1287,9 +1287,9 @@ define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, 128 - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } @@ -1297,9 +1297,9 @@ define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add nsw i32 %0, 5 - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1307,9 +1307,9 @@ define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %add = add nsw i32 %0, %x - store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + store i32 %add, i32* %add.ptr, align 4 ret void } @@ -1317,9 +1317,9 @@ define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %sub = sub nsw i32 %0, %x - store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + store i32 %sub, i32* %add.ptr, align 4 ret void } @@ -1327,9 +1327,9 @@ define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, %x - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } @@ -1337,9 +1337,9 @@ define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, %x - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1347,9 +1347,9 @@ define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %and = and i32 %0, -33 - store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + store i32 %and, i32* %add.ptr, align 4 ret void } @@ -1357,13 +1357,8 @@ define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4, !tbaa !3 + %0 = load i32* %add.ptr, align 4 %or = or i32 %0, 128 - store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + store i32 %or, i32* %add.ptr, align 4 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} -!2 = metadata !{metadata !"short", metadata !0} -!3 = metadata !{metadata !"int", metadata !0} |