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| author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
| commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
| tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/MSP430 | |
| parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
| download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 | |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/MSP430')
| -rw-r--r-- | test/CodeGen/MSP430/fp.ll | 12 | ||||
| -rw-r--r-- | test/CodeGen/MSP430/misched-msp430.ll | 20 |
2 files changed, 32 insertions, 0 deletions
diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll index 0180905..b6ba22e 100644 --- a/test/CodeGen/MSP430/fp.ll +++ b/test/CodeGen/MSP430/fp.ll @@ -15,3 +15,15 @@ entry: ; CHECK: pop.w r4 ret void } + +; Due to FPB not being marked as reserved, the register allocator used to select +; r4 as the register for the "r" constraint below. This test verifies that this +; does not happen anymore. Note that the only reason an ISR is used here is that +; the register allocator selects r4 first instead of fifth in a normal function. +define msp430_intrcc void @fpb_alloced() #0 { +; CHECK_LABEL: fpb_alloced: +; CHECK-NOT: mov.b #0, r4 +; CHECK: nop + call void asm sideeffect "nop", "r"(i8 0) + ret void +} diff --git a/test/CodeGen/MSP430/misched-msp430.ll b/test/CodeGen/MSP430/misched-msp430.ll new file mode 100644 index 0000000..c8541ef --- /dev/null +++ b/test/CodeGen/MSP430/misched-msp430.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mtriple=msp430-unknown-unknown -enable-misched | FileCheck %s + +target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" + +@y = common global i16 0, align 2 +@x = common global i16 0, align 2 + +; Test that the MI Scheduler's initPolicy does not crash when i32 is +; unsupported. The content of the asm check below is unimportant. It +; only verifies that the code generator ran successfully. +; +; CHECK-LABEL: @f +; CHECK: mov.w &y, &x +; CHECK: ret +define void @f() { +entry: + %0 = load i16* @y, align 2 + store i16 %0, i16* @x, align 2 + ret void +} |