diff options
| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/CodeGen/MSP430 | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/CodeGen/MSP430')
| -rw-r--r-- | test/CodeGen/MSP430/fp.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll index b6ba22e..2559e23 100644 --- a/test/CodeGen/MSP430/fp.ll +++ b/test/CodeGen/MSP430/fp.ll @@ -21,7 +21,7 @@ entry: ; does not happen anymore. Note that the only reason an ISR is used here is that ; the register allocator selects r4 first instead of fifth in a normal function. define msp430_intrcc void @fpb_alloced() #0 { -; CHECK_LABEL: fpb_alloced: +; CHECK-LABEL: fpb_alloced: ; CHECK-NOT: mov.b #0, r4 ; CHECK: nop call void asm sideeffect "nop", "r"(i8 0) |