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| author | Stephen Hines <srhines@google.com> | 2014-12-04 19:51:48 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2014-12-04 19:51:48 +0000 |
| commit | a21bbdfad461e957fa42ac9d6860ddc9de2da3e9 (patch) | |
| tree | 8d32ff2094b47e15a8def30d62fd7dee6e009de3 /test/CodeGen/Mips/inlineasm-operand-code.ll | |
| parent | 6b8c6a5088c221af2b25065b8b6b8b0fec8a116f (diff) | |
| parent | 876d6995443e99d13696f3941c3a789a4daa7c7a (diff) | |
| download | external_llvm-a21bbdfad461e957fa42ac9d6860ddc9de2da3e9.zip external_llvm-a21bbdfad461e957fa42ac9d6860ddc9de2da3e9.tar.gz external_llvm-a21bbdfad461e957fa42ac9d6860ddc9de2da3e9.tar.bz2 | |
am 876d6995: Merge "Update aosp/master LLVM for rebase to r222494."
* commit '876d6995443e99d13696f3941c3a789a4daa7c7a':
Update aosp/master LLVM for rebase to r222494.
Diffstat (limited to 'test/CodeGen/Mips/inlineasm-operand-code.ll')
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-operand-code.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index 6512851..3d9dec7 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -65,6 +65,33 @@ entry: ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0 ;CHECK_LITTLE_32: #NO_APP tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind + +; z with non-zero and the "r"(register) and "J"(integer zero) constraints +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP + call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind + +; z with zero and the "r"(register) and "J"(integer zero) constraints +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP + call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind + +; z with non-zero and just the "r"(register) constraint +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP + call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind + +; z with zero and just the "r"(register) constraint +; FIXME: Check for $0, instead of other registers. +; We should be using $0 directly in this case, not real registers. +; When the materialization of 0 gets fixed, this test will fail. +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP + call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind ret i32 0 } |