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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/CodeGen/Mips/inlineasm_constraint.ll | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/CodeGen/Mips/inlineasm_constraint.ll')
| -rw-r--r-- | test/CodeGen/Mips/inlineasm_constraint.ll | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index 8d30f45..76b73dc 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -5,21 +5,21 @@ entry: ; First I with short ; CHECK: #APP -; CHECK: addi ${{[0-9]+}},${{[0-9]+}},4096 +; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096 ; CHECK: #NO_APP - tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind + tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind ; Then I with int ; CHECK: #APP -; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind + tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind ; Now J with 0 ; CHECK: #APP -; CHECK: addi ${{[0-9]+}},${{[0-9]+}},0 +; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addi $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind + tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind ; Now K with 64 ; CHECK: #APP @@ -35,29 +35,29 @@ entry: ; Now N with -3 ; CHECK: #APP -; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind + tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind ; Now O with -3 ; CHECK: #APP -; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind + tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind ; Now P with 65535 ; CHECK: #APP -; CHECK: addi ${{[0-9]+}},${{[0-9]+}},65535 +; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},65535 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind + tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind ; Now R Which takes the address of c %c = alloca i32, align 4 store i32 -4469539, i32* %c, align 4 - %8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1 + %8 = call i32 asm sideeffect "lw $0, 1 + $1\0A\09lw $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1 ; CHECK: #APP -; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}}) -; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}}) +; CHECK: lw ${{[0-9]+}}, 1 + 0(${{[0-9]+}}) +; CHECK: lw ${{[0-9]+}}, 2 + 0(${{[0-9]+}}) ; CHECK: #NO_APP ret i32 0 |