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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Mips/mips64intldst.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/Mips/mips64intldst.ll')
| -rw-r--r-- | test/CodeGen/Mips/mips64intldst.ll | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/test/CodeGen/Mips/mips64intldst.ll b/test/CodeGen/Mips/mips64intldst.ll index 1ceafc1..658ab88 100644 --- a/test/CodeGen/Mips/mips64intldst.ll +++ b/test/CodeGen/Mips/mips64intldst.ll @@ -20,7 +20,7 @@ entry: ; CHECK-N32: func1 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]]) - %0 = load i8* @c, align 4 + %0 = load i8, i8* @c, align 4 %conv = sext i8 %0 to i64 ret i64 %conv } @@ -33,7 +33,7 @@ entry: ; CHECK-N32: func2 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]]) - %0 = load i16* @s, align 4 + %0 = load i16, i16* @s, align 4 %conv = sext i16 %0 to i64 ret i64 %conv } @@ -46,7 +46,7 @@ entry: ; CHECK-N32: func3 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]]) - %0 = load i32* @i, align 4 + %0 = load i32, i32* @i, align 4 %conv = sext i32 %0 to i64 ret i64 %conv } @@ -59,7 +59,7 @@ entry: ; CHECK-N32: func4 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]]) - %0 = load i64* @l, align 8 + %0 = load i64, i64* @l, align 8 ret i64 %0 } @@ -71,7 +71,7 @@ entry: ; CHECK-N32: ufunc1 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc) ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]]) - %0 = load i8* @uc, align 4 + %0 = load i8, i8* @uc, align 4 %conv = zext i8 %0 to i64 ret i64 %conv } @@ -84,7 +84,7 @@ entry: ; CHECK-N32: ufunc2 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us) ; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]]) - %0 = load i16* @us, align 4 + %0 = load i16, i16* @us, align 4 %conv = zext i16 %0 to i64 ret i64 %conv } @@ -97,7 +97,7 @@ entry: ; CHECK-N32: ufunc3 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui) ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]]) - %0 = load i32* @ui, align 4 + %0 = load i32, i32* @ui, align 4 %conv = zext i32 %0 to i64 ret i64 %conv } @@ -110,7 +110,7 @@ entry: ; CHECK-N32: sfunc1 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c) ; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]]) - %0 = load i64* @l1, align 8 + %0 = load i64, i64* @l1, align 8 %conv = trunc i64 %0 to i8 store i8 %conv, i8* @c, align 4 ret void @@ -124,7 +124,7 @@ entry: ; CHECK-N32: sfunc2 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s) ; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]]) - %0 = load i64* @l1, align 8 + %0 = load i64, i64* @l1, align 8 %conv = trunc i64 %0 to i16 store i16 %conv, i16* @s, align 4 ret void @@ -138,7 +138,7 @@ entry: ; CHECK-N32: sfunc3 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i) ; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]]) - %0 = load i64* @l1, align 8 + %0 = load i64, i64* @l1, align 8 %conv = trunc i64 %0 to i32 store i32 %conv, i32* @i, align 4 ret void @@ -152,7 +152,7 @@ entry: ; CHECK-N32: sfunc4 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l) ; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]]) - %0 = load i64* @l1, align 8 + %0 = load i64, i64* @l1, align 8 store i64 %0, i64* @l, align 8 ret void } |