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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-19 19:44:09 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-19 19:44:09 +0000 |
| commit | ee973147ac0aad6471f5506c3278654baec4d1c0 (patch) | |
| tree | 93a2e440fd57de9e73c31c0ebd2fabce2ded2242 /test/CodeGen/Mips/mips64shift.ll | |
| parent | 6849019079794c573b72c1ec55613cb6ba1297a5 (diff) | |
| download | external_llvm-ee973147ac0aad6471f5506c3278654baec4d1c0.zip external_llvm-ee973147ac0aad6471f5506c3278654baec4d1c0.tar.gz external_llvm-ee973147ac0aad6471f5506c3278654baec4d1c0.tar.bz2 | |
Remove definitions of double word shift plus 32 instructions. Assembler or
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/mips64shift.ll')
| -rw-r--r-- | test/CodeGen/Mips/mips64shift.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll index cc5e508..45d1c95 100644 --- a/test/CodeGen/Mips/mips64shift.ll +++ b/test/CodeGen/Mips/mips64shift.ll @@ -44,21 +44,21 @@ entry: define i64 @f6(i64 %a0) nounwind readnone { entry: -; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 %shl = shl i64 %a0, 40 ret i64 %shl } define i64 @f7(i64 %a0) nounwind readnone { entry: -; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = ashr i64 %a0, 40 ret i64 %shr } define i64 @f8(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8 +; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = lshr i64 %a0, 40 ret i64 %shr } @@ -94,7 +94,7 @@ entry: define i64 @f12(i64 %a0) nounwind readnone { entry: -; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22 +; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 %shl = shl i64 %a0, 10 %shr = lshr i64 %a0, 54 %or = or i64 %shl, %shr |