am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"

* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
  Update aosp/master llvm for rebase to r233350

1 files changed, 96 insertions, 96 deletions

diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll
index dab15b6..db772f9 100644
--- a/test/CodeGen/Mips/msa/3r-a.ll
+++ b/test/CodeGen/Mips/msa/3r-a.ll
@@ -15,8 +15,8 @@
 
 define void @llvm_mips_add_a_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_add_a_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_add_a_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_add_a_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_add_a_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.add.a.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_add_a_b_RES
   ret void
@@ -40,8 +40,8 @@ declare <16 x i8> @llvm.mips.add.a.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_add_a_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_add_a_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_add_a_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_add_a_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_add_a_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.add.a.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_add_a_h_RES
   ret void
@@ -65,8 +65,8 @@ declare <8 x i16> @llvm.mips.add.a.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_add_a_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_add_a_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_add_a_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_add_a_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_add_a_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.add.a.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_add_a_w_RES
   ret void
@@ -90,8 +90,8 @@ declare <4 x i32> @llvm.mips.add.a.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_add_a_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_add_a_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_add_a_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_add_a_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_add_a_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.add.a.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_add_a_d_RES
   ret void
@@ -115,8 +115,8 @@ declare <2 x i64> @llvm.mips.add.a.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_adds_a_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_adds_a_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_adds_a_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_a_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_a_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.adds.a.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_a_b_RES
   ret void
@@ -140,8 +140,8 @@ declare <16 x i8> @llvm.mips.adds.a.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_adds_a_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_adds_a_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_adds_a_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_a_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_a_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.adds.a.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_a_h_RES
   ret void
@@ -165,8 +165,8 @@ declare <8 x i16> @llvm.mips.adds.a.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_adds_a_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_adds_a_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_adds_a_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_a_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_a_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.adds.a.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_a_w_RES
   ret void
@@ -190,8 +190,8 @@ declare <4 x i32> @llvm.mips.adds.a.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_adds_a_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_adds_a_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_adds_a_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_a_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_a_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.adds.a.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_a_d_RES
   ret void
@@ -215,8 +215,8 @@ declare <2 x i64> @llvm.mips.adds.a.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_adds_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_adds_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_adds_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.adds.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_s_b_RES
   ret void
@@ -240,8 +240,8 @@ declare <16 x i8> @llvm.mips.adds.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_adds_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_adds_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_adds_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.adds.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_s_h_RES
   ret void
@@ -265,8 +265,8 @@ declare <8 x i16> @llvm.mips.adds.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_adds_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_adds_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_adds_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.adds.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_s_w_RES
   ret void
@@ -290,8 +290,8 @@ declare <4 x i32> @llvm.mips.adds.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_adds_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_adds_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_adds_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.adds.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_s_d_RES
   ret void
@@ -315,8 +315,8 @@ declare <2 x i64> @llvm.mips.adds.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_adds_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_adds_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_adds_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_adds_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.adds.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_u_b_RES
   ret void
@@ -340,8 +340,8 @@ declare <16 x i8> @llvm.mips.adds.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_adds_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_adds_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_adds_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_adds_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.adds.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_u_h_RES
   ret void
@@ -365,8 +365,8 @@ declare <8 x i16> @llvm.mips.adds.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_adds_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_adds_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_adds_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_adds_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.adds.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_u_w_RES
   ret void
@@ -390,8 +390,8 @@ declare <4 x i32> @llvm.mips.adds.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_adds_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_adds_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_adds_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_adds_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.adds.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_u_d_RES
   ret void
@@ -415,8 +415,8 @@ declare <2 x i64> @llvm.mips.adds.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_addv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES
   ret void
@@ -440,8 +440,8 @@ declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_addv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES
   ret void
@@ -465,8 +465,8 @@ declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_addv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES
   ret void
@@ -490,8 +490,8 @@ declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_addv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES
   ret void
@@ -512,8 +512,8 @@ declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @addv_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_addv_b_ARG2
   %2 = add <16 x i8> %0, %1
   store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES
   ret void
@@ -532,8 +532,8 @@ entry:
 
 define void @addv_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_addv_h_ARG2
   %2 = add <8 x i16> %0, %1
   store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES
   ret void
@@ -552,8 +552,8 @@ entry:
 
 define void @addv_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_addv_w_ARG2
   %2 = add <4 x i32> %0, %1
   store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES
   ret void
@@ -572,8 +572,8 @@ entry:
 
 define void @addv_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_addv_d_ARG2
   %2 = add <2 x i64> %0, %1
   store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES
   ret void
@@ -595,8 +595,8 @@ entry:
 
 define void @llvm_mips_asub_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_asub_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_asub_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.asub.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_asub_s_b_RES
   ret void
@@ -620,8 +620,8 @@ declare <16 x i8> @llvm.mips.asub.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_asub_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_asub_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_asub_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.asub.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_asub_s_h_RES
   ret void
@@ -645,8 +645,8 @@ declare <8 x i16> @llvm.mips.asub.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_asub_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_asub_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_asub_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.asub.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_asub_s_w_RES
   ret void
@@ -670,8 +670,8 @@ declare <4 x i32> @llvm.mips.asub.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_asub_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_asub_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_asub_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.asub.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_asub_s_d_RES
   ret void
@@ -695,8 +695,8 @@ declare <2 x i64> @llvm.mips.asub.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_asub_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_asub_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_asub_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_asub_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.asub.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_asub_u_b_RES
   ret void
@@ -720,8 +720,8 @@ declare <16 x i8> @llvm.mips.asub.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_asub_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_asub_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_asub_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_asub_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.asub.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_asub_u_h_RES
   ret void
@@ -745,8 +745,8 @@ declare <8 x i16> @llvm.mips.asub.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_asub_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_asub_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_asub_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_asub_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.asub.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_asub_u_w_RES
   ret void
@@ -770,8 +770,8 @@ declare <4 x i32> @llvm.mips.asub.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_asub_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_asub_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_asub_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_asub_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.asub.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_asub_u_d_RES
   ret void
@@ -795,8 +795,8 @@ declare <2 x i64> @llvm.mips.asub.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ave_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ave_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ave_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ave.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ave_s_b_RES
   ret void
@@ -820,8 +820,8 @@ declare <16 x i8> @llvm.mips.ave.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ave_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ave_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ave_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ave.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ave_s_h_RES
   ret void
@@ -845,8 +845,8 @@ declare <8 x i16> @llvm.mips.ave.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ave_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ave_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ave_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ave.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ave_s_w_RES
   ret void
@@ -870,8 +870,8 @@ declare <4 x i32> @llvm.mips.ave.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ave_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ave_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ave_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ave.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ave_s_d_RES
   ret void
@@ -895,8 +895,8 @@ declare <2 x i64> @llvm.mips.ave.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_ave_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_ave_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_ave_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_ave_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.ave.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_ave_u_b_RES
   ret void
@@ -920,8 +920,8 @@ declare <16 x i8> @llvm.mips.ave.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_ave_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_ave_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_ave_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_ave_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.ave.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_ave_u_h_RES
   ret void
@@ -945,8 +945,8 @@ declare <8 x i16> @llvm.mips.ave.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_ave_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_ave_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_ave_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_ave_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.ave.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_ave_u_w_RES
   ret void
@@ -970,8 +970,8 @@ declare <4 x i32> @llvm.mips.ave.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_ave_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_ave_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_ave_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_ave_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.ave.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_ave_u_d_RES
   ret void
@@ -995,8 +995,8 @@ declare <2 x i64> @llvm.mips.ave.u.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_aver_s_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_aver_s_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_aver_s_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_s_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_s_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.aver.s.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_aver_s_b_RES
   ret void
@@ -1020,8 +1020,8 @@ declare <16 x i8> @llvm.mips.aver.s.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_aver_s_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_aver_s_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_aver_s_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_s_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_s_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.aver.s.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_aver_s_h_RES
   ret void
@@ -1045,8 +1045,8 @@ declare <8 x i16> @llvm.mips.aver.s.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_aver_s_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_aver_s_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_aver_s_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_s_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_s_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.aver.s.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_aver_s_w_RES
   ret void
@@ -1070,8 +1070,8 @@ declare <4 x i32> @llvm.mips.aver.s.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_aver_s_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_aver_s_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_aver_s_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_s_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_s_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.aver.s.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_aver_s_d_RES
   ret void
@@ -1095,8 +1095,8 @@ declare <2 x i64> @llvm.mips.aver.s.d(<2 x i64>, <2 x i64>) nounwind
 
 define void @llvm_mips_aver_u_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_aver_u_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_aver_u_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_u_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_aver_u_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.aver.u.b(<16 x i8> %0, <16 x i8> %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_aver_u_b_RES
   ret void
@@ -1120,8 +1120,8 @@ declare <16 x i8> @llvm.mips.aver.u.b(<16 x i8>, <16 x i8>) nounwind
 
 define void @llvm_mips_aver_u_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_aver_u_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_aver_u_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_u_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_aver_u_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.aver.u.h(<8 x i16> %0, <8 x i16> %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_aver_u_h_RES
   ret void
@@ -1145,8 +1145,8 @@ declare <8 x i16> @llvm.mips.aver.u.h(<8 x i16>, <8 x i16>) nounwind
 
 define void @llvm_mips_aver_u_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_aver_u_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_aver_u_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_u_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_aver_u_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.aver.u.w(<4 x i32> %0, <4 x i32> %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_aver_u_w_RES
   ret void
@@ -1170,8 +1170,8 @@ declare <4 x i32> @llvm.mips.aver.u.w(<4 x i32>, <4 x i32>) nounwind
 
 define void @llvm_mips_aver_u_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_aver_u_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_aver_u_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_u_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_aver_u_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.aver.u.d(<2 x i64> %0, <2 x i64> %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_aver_u_d_RES
   ret void