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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Mips/msa/3r_splat.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/Mips/msa/3r_splat.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/3r_splat.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll index 6b0cb26..56d26b0 100644 --- a/test/CodeGen/Mips/msa/3r_splat.ll +++ b/test/CodeGen/Mips/msa/3r_splat.ll @@ -11,7 +11,7 @@ define void @llvm_mips_splat_b_test(i32 %a) nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_splat_b_ARG1 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_splat_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a) store <16 x i8> %1, <16 x i8>* @llvm_mips_splat_b_RES ret void @@ -32,7 +32,7 @@ declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind define void @llvm_mips_splat_h_test(i32 %a) nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_splat_h_ARG1 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_splat_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a) store <8 x i16> %1, <8 x i16>* @llvm_mips_splat_h_RES ret void @@ -53,7 +53,7 @@ declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind define void @llvm_mips_splat_w_test(i32 %a) nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_splat_w_ARG1 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_splat_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a) store <4 x i32> %1, <4 x i32>* @llvm_mips_splat_w_RES ret void @@ -74,7 +74,7 @@ declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind define void @llvm_mips_splat_d_test(i32 %a) nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_splat_d_ARG1 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_splat_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.splat.d(<2 x i64> %0, i32 %a) store <2 x i64> %1, <2 x i64>* @llvm_mips_splat_d_RES ret void |