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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Mips/msa/3rf_4rf.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/Mips/msa/3rf_4rf.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/3rf_4rf.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/Mips/msa/3rf_4rf.ll b/test/CodeGen/Mips/msa/3rf_4rf.ll index 67ef7fd..f1a3002 100644 --- a/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -11,9 +11,9 @@ define void @llvm_mips_fmadd_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_fmadd_w_ARG1 - %1 = load <4 x float>* @llvm_mips_fmadd_w_ARG2 - %2 = load <4 x float>* @llvm_mips_fmadd_w_ARG3 + %0 = load <4 x float>, <4 x float>* @llvm_mips_fmadd_w_ARG1 + %1 = load <4 x float>, <4 x float>* @llvm_mips_fmadd_w_ARG2 + %2 = load <4 x float>, <4 x float>* @llvm_mips_fmadd_w_ARG3 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2) store <4 x float> %3, <4 x float>* @llvm_mips_fmadd_w_RES ret void @@ -36,9 +36,9 @@ declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) no define void @llvm_mips_fmadd_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_fmadd_d_ARG1 - %1 = load <2 x double>* @llvm_mips_fmadd_d_ARG2 - %2 = load <2 x double>* @llvm_mips_fmadd_d_ARG3 + %0 = load <2 x double>, <2 x double>* @llvm_mips_fmadd_d_ARG1 + %1 = load <2 x double>, <2 x double>* @llvm_mips_fmadd_d_ARG2 + %2 = load <2 x double>, <2 x double>* @llvm_mips_fmadd_d_ARG3 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2) store <2 x double> %3, <2 x double>* @llvm_mips_fmadd_d_RES ret void @@ -61,9 +61,9 @@ declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double> define void @llvm_mips_fmsub_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_fmsub_w_ARG1 - %1 = load <4 x float>* @llvm_mips_fmsub_w_ARG2 - %2 = load <4 x float>* @llvm_mips_fmsub_w_ARG3 + %0 = load <4 x float>, <4 x float>* @llvm_mips_fmsub_w_ARG1 + %1 = load <4 x float>, <4 x float>* @llvm_mips_fmsub_w_ARG2 + %2 = load <4 x float>, <4 x float>* @llvm_mips_fmsub_w_ARG3 %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2) store <4 x float> %3, <4 x float>* @llvm_mips_fmsub_w_RES ret void @@ -86,9 +86,9 @@ declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) no define void @llvm_mips_fmsub_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_fmsub_d_ARG1 - %1 = load <2 x double>* @llvm_mips_fmsub_d_ARG2 - %2 = load <2 x double>* @llvm_mips_fmsub_d_ARG3 + %0 = load <2 x double>, <2 x double>* @llvm_mips_fmsub_d_ARG1 + %1 = load <2 x double>, <2 x double>* @llvm_mips_fmsub_d_ARG2 + %2 = load <2 x double>, <2 x double>* @llvm_mips_fmsub_d_ARG3 %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2) store <2 x double> %3, <2 x double>* @llvm_mips_fmsub_d_RES ret void |