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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/Mips/msa/elm_insv.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/Mips/msa/elm_insv.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/elm_insv.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll index c746e52..46e6289 100644 --- a/test/CodeGen/Mips/msa/elm_insv.ll +++ b/test/CodeGen/Mips/msa/elm_insv.ll @@ -16,8 +16,8 @@ define void @llvm_mips_insert_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_insert_b_ARG1 - %1 = load i32* @llvm_mips_insert_b_ARG3 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_insert_b_ARG1 + %1 = load i32, i32* @llvm_mips_insert_b_ARG3 %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_insert_b_RES ret void @@ -38,8 +38,8 @@ declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind define void @llvm_mips_insert_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_insert_h_ARG1 - %1 = load i32* @llvm_mips_insert_h_ARG3 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_insert_h_ARG1 + %1 = load i32, i32* @llvm_mips_insert_h_ARG3 %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_insert_h_RES ret void @@ -60,8 +60,8 @@ declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind define void @llvm_mips_insert_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_insert_w_ARG1 - %1 = load i32* @llvm_mips_insert_w_ARG3 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_insert_w_ARG1 + %1 = load i32, i32* @llvm_mips_insert_w_ARG3 %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_insert_w_RES ret void @@ -82,8 +82,8 @@ declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind define void @llvm_mips_insert_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_insert_d_ARG1 - %1 = load i64* @llvm_mips_insert_d_ARG3 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_insert_d_ARG1 + %1 = load i64, i64* @llvm_mips_insert_d_ARG3 %2 = tail call <2 x i64> @llvm.mips.insert.d(<2 x i64> %0, i32 1, i64 %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_insert_d_RES ret void @@ -110,8 +110,8 @@ declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind define void @llvm_mips_insve_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_insve_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_insve_b_ARG3 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_insve_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_insve_b_ARG3 %2 = tail call <16 x i8> @llvm.mips.insve.b(<16 x i8> %0, i32 1, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_insve_b_RES ret void @@ -136,8 +136,8 @@ declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind define void @llvm_mips_insve_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_insve_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_insve_h_ARG3 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_insve_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_insve_h_ARG3 %2 = tail call <8 x i16> @llvm.mips.insve.h(<8 x i16> %0, i32 1, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_insve_h_RES ret void @@ -162,8 +162,8 @@ declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind define void @llvm_mips_insve_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_insve_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_insve_w_ARG3 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_insve_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_insve_w_ARG3 %2 = tail call <4 x i32> @llvm.mips.insve.w(<4 x i32> %0, i32 1, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_insve_w_RES ret void @@ -188,8 +188,8 @@ declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind define void @llvm_mips_insve_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_insve_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_insve_d_ARG3 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_insve_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_insve_d_ARG3 %2 = tail call <2 x i64> @llvm.mips.insve.d(<2 x i64> %0, i32 1, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_insve_d_RES ret void |