am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"

* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
  Update aosp/master llvm for rebase to r233350

1 files changed, 28 insertions, 28 deletions

diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll
index da6be66..40ab095 100644
--- a/test/CodeGen/Mips/msa/i5-b.ll
+++ b/test/CodeGen/Mips/msa/i5-b.ll
@@ -9,7 +9,7 @@
 
 define void @llvm_mips_bclri_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bclri_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bclri_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_bclri_b_RES
   ret void
@@ -29,7 +29,7 @@ declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bclri_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bclri_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bclri_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_bclri_h_RES
   ret void
@@ -48,7 +48,7 @@ declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_bclri_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bclri_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bclri_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_bclri_w_RES
   ret void
@@ -67,7 +67,7 @@ declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_bclri_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bclri_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bclri_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_bclri_d_RES
   ret void
@@ -87,8 +87,8 @@ declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_binsli_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_binsli_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_binsli_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES
   ret void
@@ -112,8 +112,8 @@ declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_binsli_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_binsli_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_binsli_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsli_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsli_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_binsli_h_RES
   ret void
@@ -137,8 +137,8 @@ declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_binsli_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_binsli_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_binsli_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsli_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsli_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_binsli_w_RES
   ret void
@@ -162,8 +162,8 @@ declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_binsli_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_binsli_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_binsli_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsli_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsli_d_ARG2
   ; TODO: We use a particularly wide mask here to work around a legalization
   ;       issue. If the mask doesn't fit within a 10-bit immediate, it gets
   ;       legalized into a constant pool. We should add a test to cover the
@@ -191,8 +191,8 @@ declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_binsri_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_binsri_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_binsri_b_ARG2
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG1
+  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG2
   %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES
   ret void
@@ -216,8 +216,8 @@ declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind
 
 define void @llvm_mips_binsri_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_binsri_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_binsri_h_ARG2
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsri_h_ARG1
+  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsri_h_ARG2
   %2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_binsri_h_RES
   ret void
@@ -241,8 +241,8 @@ declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind
 
 define void @llvm_mips_binsri_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_binsri_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_binsri_w_ARG2
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsri_w_ARG1
+  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsri_w_ARG2
   %2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_binsri_w_RES
   ret void
@@ -266,8 +266,8 @@ declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind
 
 define void @llvm_mips_binsri_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_binsri_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_binsri_d_ARG2
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsri_d_ARG1
+  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsri_d_ARG2
   %2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_binsri_d_RES
   ret void
@@ -290,7 +290,7 @@ declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind
 
 define void @llvm_mips_bnegi_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bnegi_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bnegi_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_bnegi_b_RES
   ret void
@@ -309,7 +309,7 @@ declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bnegi_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bnegi_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bnegi_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_bnegi_h_RES
   ret void
@@ -328,7 +328,7 @@ declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_bnegi_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bnegi_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bnegi_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_bnegi_w_RES
   ret void
@@ -347,7 +347,7 @@ declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_bnegi_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bnegi_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bnegi_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_bnegi_d_RES
   ret void
@@ -366,7 +366,7 @@ declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32) nounwind
 
 define void @llvm_mips_bseti_b_test() nounwind {
 entry:
-  %0 = load <16 x i8>* @llvm_mips_bseti_b_ARG1
+  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bseti_b_ARG1
   %1 = tail call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %0, i32 7)
   store <16 x i8> %1, <16 x i8>* @llvm_mips_bseti_b_RES
   ret void
@@ -385,7 +385,7 @@ declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32) nounwind
 
 define void @llvm_mips_bseti_h_test() nounwind {
 entry:
-  %0 = load <8 x i16>* @llvm_mips_bseti_h_ARG1
+  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bseti_h_ARG1
   %1 = tail call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %0, i32 7)
   store <8 x i16> %1, <8 x i16>* @llvm_mips_bseti_h_RES
   ret void
@@ -404,7 +404,7 @@ declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32) nounwind
 
 define void @llvm_mips_bseti_w_test() nounwind {
 entry:
-  %0 = load <4 x i32>* @llvm_mips_bseti_w_ARG1
+  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bseti_w_ARG1
   %1 = tail call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %0, i32 7)
   store <4 x i32> %1, <4 x i32>* @llvm_mips_bseti_w_RES
   ret void
@@ -423,7 +423,7 @@ declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32) nounwind
 
 define void @llvm_mips_bseti_d_test() nounwind {
 entry:
-  %0 = load <2 x i64>* @llvm_mips_bseti_d_ARG1
+  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bseti_d_ARG1
   %1 = tail call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %0, i32 7)
   store <2 x i64> %1, <2 x i64>* @llvm_mips_bseti_d_RES
   ret void