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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-11 17:23:41 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-11 17:23:41 +0000 |
| commit | 028e4d27b1afc62be0687e9c3b57992c36852938 (patch) | |
| tree | 3622a9691dfecf043d2aa73aecad098ebc7c0275 /test/CodeGen/Mips/msa | |
| parent | 12f06e1e0936b01bf329615ec4f0f5488c98c0dd (diff) | |
| download | external_llvm-028e4d27b1afc62be0687e9c3b57992c36852938.zip external_llvm-028e4d27b1afc62be0687e9c3b57992c36852938.tar.gz external_llvm-028e4d27b1afc62be0687e9c3b57992c36852938.tar.bz2 | |
Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too
Reviewers: dsanders
Reviewed By: dsanders
CC: llvm-commits, nadav
Differential Revision: http://llvm-reviews.chandlerc.com/D1958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa')
| -rw-r--r-- | test/CodeGen/Mips/msa/shift-dagcombine.ll | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/shift-dagcombine.ll b/test/CodeGen/Mips/msa/shift-dagcombine.ll new file mode 100644 index 0000000..0d809fb --- /dev/null +++ b/test/CodeGen/Mips/msa/shift-dagcombine.ll @@ -0,0 +1,70 @@ +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s + +define void @ashr_v4i32(<4 x i32>* %c) nounwind { + ; CHECK-LABEL: ashr_v4i32: + + %1 = ashr <4 x i32> <i32 1, i32 2, i32 4, i32 8>, + <i32 0, i32 1, i32 2, i32 3> + ; CHECK-NOT: sra + ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1 + ; CHECK-NOT: sra + store volatile <4 x i32> %1, <4 x i32>* %c + ; CHECK-DAG: st.w [[R1]], 0($4) + + %2 = ashr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>, + <i32 0, i32 1, i32 2, i32 3> + ; CHECK-NOT: sra + ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -2 + ; CHECK-NOT: sra + store volatile <4 x i32> %2, <4 x i32>* %c + ; CHECK-DAG: st.w [[R1]], 0($4) + + ret void + ; CHECK-LABEL: .size ashr_v4i32 +} + +define void @lshr_v4i32(<4 x i32>* %c) nounwind { + ; CHECK-LABEL: lshr_v4i32: + + %1 = lshr <4 x i32> <i32 1, i32 2, i32 4, i32 8>, + <i32 0, i32 1, i32 2, i32 3> + ; CHECK-NOT: srl + ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1 + ; CHECK-NOT: srl + store volatile <4 x i32> %1, <4 x i32>* %c + ; CHECK-DAG: st.w [[R1]], 0($4) + + %2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>, + <i32 0, i32 1, i32 2, i32 3> + ; CHECK-NOT: srl + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], %lo + ; CHECK-NOT: srl + store volatile <4 x i32> %2, <4 x i32>* %c + ; CHECK-DAG: st.w [[R1]], 0($4) + + ret void + ; CHECK-LABEL: .size lshr_v4i32 +} + +define void @shl_v4i32(<4 x i32>* %c) nounwind { + ; CHECK-LABEL: shl_v4i32: + + %1 = shl <4 x i32> <i32 8, i32 4, i32 2, i32 1>, + <i32 0, i32 1, i32 2, i32 3> + ; CHECK-NOT: sll + ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 8 + ; CHECK-NOT: sll + store volatile <4 x i32> %1, <4 x i32>* %c + ; CHECK-DAG: st.w [[R1]], 0($4) + + %2 = shl <4 x i32> <i32 -8, i32 -4, i32 -2, i32 -1>, + <i32 0, i32 1, i32 2, i32 3> + ; CHECK-NOT: sll + ; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -8 + ; CHECK-NOT: sll + store volatile <4 x i32> %2, <4 x i32>* %c + ; CHECK-DAG: st.w [[R1]], 0($4) + + ret void + ; CHECK-LABEL: .size shl_v4i32 +} |