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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-10-11 10:27:32 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-10-11 10:27:32 +0000 |
| commit | 4fa2c32220405ac32838e45d91392a83fae70bb0 (patch) | |
| tree | f4d3fca94d76642994cf0cc6ce995f7a164b3eb1 /test/CodeGen/Mips/msa | |
| parent | ed0ed946ab6b84814ba09a6224d1ec4bfb9447b1 (diff) | |
| download | external_llvm-4fa2c32220405ac32838e45d91392a83fae70bb0.zip external_llvm-4fa2c32220405ac32838e45d91392a83fae70bb0.tar.gz external_llvm-4fa2c32220405ac32838e45d91392a83fae70bb0.tar.bz2 | |
[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/msa')
| -rw-r--r-- | test/CodeGen/Mips/msa/arithmetic_float.ll | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index 70167ef..4392c77 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -136,6 +136,46 @@ define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, ; CHECK: .size fma_v2f64 } +define void @fmsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, + <4 x float>* %c) nounwind { + ; CHECK: fmsub_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x float>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = load <4 x float>* %c + ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) + %4 = fmul <4 x float> %2, %3 + %5 = fsub <4 x float> %1, %4 + ; CHECK-DAG: fmsub.w [[R1]], [[R2]], [[R3]] + store <4 x float> %5, <4 x float>* %d + ; CHECK-DAG: st.w [[R1]], 0($4) + + ret void + ; CHECK: .size fmsub_v4f32 +} + +define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, + <2 x double>* %c) nounwind { + ; CHECK: fmsub_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x double>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = load <2 x double>* %c + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) + %4 = fmul <2 x double> %2, %3 + %5 = fsub <2 x double> %1, %4 + ; CHECK-DAG: fmsub.d [[R1]], [[R2]], [[R3]] + store <2 x double> %5, <2 x double>* %d + ; CHECK-DAG: st.d [[R1]], 0($4) + + ret void + ; CHECK: .size fmsub_v2f64 +} + define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { ; CHECK: fdiv_v4f32: |