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author | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-09 20:45:50 +0000 |
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committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-09 20:45:50 +0000 |
commit | 8ddf6531b88937dec35bf2bb3a55245b1af9cbf5 (patch) | |
tree | b02f180f3b69779d7e4915457516d4c04c34c8b7 /test/CodeGen/Mips/select.ll | |
parent | 8ffad56f8eb41c73ecf40d1aa473819eb6915c12 (diff) | |
download | external_llvm-8ddf6531b88937dec35bf2bb3a55245b1af9cbf5.zip external_llvm-8ddf6531b88937dec35bf2bb3a55245b1af9cbf5.tar.gz external_llvm-8ddf6531b88937dec35bf2bb3a55245b1af9cbf5.tar.bz2 |
Drop support for Mips1 and Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/select.ll')
-rw-r--r-- | test/CodeGen/Mips/select.ll | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index 623c2a3..e79d65f 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2 -; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1 @d2 = external global double @d3 = external global double @@ -7,7 +6,6 @@ define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone { entry: ; CHECK-MIPS32R2: movn -; CHECK-MIPS1: beq %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, i32 %f1, i32 %f0 ret i32 %cond @@ -16,7 +14,6 @@ entry: define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone { entry: ; CHECK-MIPS32R2: movn.s -; CHECK-MIPS1: beq %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, float %f0, float %f1 ret float %cond @@ -25,7 +22,6 @@ entry: define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone { entry: ; CHECK-MIPS32R2: movn.d -; CHECK-MIPS1: bne %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, double %f0, double %f1 ret double %cond @@ -35,8 +31,6 @@ define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone entry: ; CHECK-MIPS32R2: c.eq.s ; CHECK-MIPS32R2: movt.s -; CHECK-MIPS1: c.eq.s -; CHECK-MIPS1: bc1f %cmp = fcmp oeq float %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -46,8 +40,6 @@ define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone entry: ; CHECK-MIPS32R2: c.olt.s ; CHECK-MIPS32R2: movt.s -; CHECK-MIPS1: c.olt.s -; CHECK-MIPS1: bc1f %cmp = fcmp olt float %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -57,8 +49,6 @@ define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone entry: ; CHECK-MIPS32R2: c.ule.s ; CHECK-MIPS32R2: movf.s -; CHECK-MIPS1: c.ule.s -; CHECK-MIPS1: bc1t %cmp = fcmp ogt float %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -68,8 +58,6 @@ define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind rea entry: ; CHECK-MIPS32R2: c.ule.s ; CHECK-MIPS32R2: movf.d -; CHECK-MIPS1: c.ule.s -; CHECK-MIPS1: bc1t %cmp = fcmp ogt float %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -79,8 +67,6 @@ define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind rea entry: ; CHECK-MIPS32R2: c.eq.d ; CHECK-MIPS32R2: movt.d -; CHECK-MIPS1: c.eq.d -; CHECK-MIPS1: bc1f %cmp = fcmp oeq double %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -90,8 +76,6 @@ define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind rea entry: ; CHECK-MIPS32R2: c.olt.d ; CHECK-MIPS32R2: movt.d -; CHECK-MIPS1: c.olt.d -; CHECK-MIPS1: bc1f %cmp = fcmp olt double %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -101,8 +85,6 @@ define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind rea entry: ; CHECK-MIPS32R2: c.ule.d ; CHECK-MIPS32R2: movf.d -; CHECK-MIPS1: c.ule.d -; CHECK-MIPS1: bc1t %cmp = fcmp ogt double %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -112,8 +94,6 @@ define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind read entry: ; CHECK-MIPS32R2: c.ule.d ; CHECK-MIPS32R2: movf.s -; CHECK-MIPS1: c.ule.d -; CHECK-MIPS1: bc1t %cmp = fcmp ogt double %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -123,8 +103,6 @@ define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { entry: ; CHECK-MIPS32R2: c.eq.s ; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.eq.s -; CHECK-MIPS1: bc1f %cmp = fcmp oeq float %f2, %f3 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -134,8 +112,6 @@ define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { entry: ; CHECK-MIPS32R2: c.olt.s ; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.olt.s -; CHECK-MIPS1: bc1f %cmp = fcmp olt float %f2, %f3 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -145,8 +121,6 @@ define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { entry: ; CHECK-MIPS32R2: c.ule.s ; CHECK-MIPS32R2: movf -; CHECK-MIPS1: c.ule.s -; CHECK-MIPS1: bc1t %cmp = fcmp ogt float %f2, %f3 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -156,8 +130,6 @@ define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly { entry: ; CHECK-MIPS32R2: c.eq.d ; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.eq.d -; CHECK-MIPS1: bc1f %tmp = load double* @d2, align 8, !tbaa !0 %tmp1 = load double* @d3, align 8, !tbaa !0 %cmp = fcmp oeq double %tmp, %tmp1 @@ -169,8 +141,6 @@ define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly { entry: ; CHECK-MIPS32R2: c.olt.d ; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.olt.d -; CHECK-MIPS1: bc1f %tmp = load double* @d2, align 8, !tbaa !0 %tmp1 = load double* @d3, align 8, !tbaa !0 %cmp = fcmp olt double %tmp, %tmp1 @@ -182,8 +152,6 @@ define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly { entry: ; CHECK-MIPS32R2: c.ule.d ; CHECK-MIPS32R2: movf -; CHECK-MIPS1: c.ule.d -; CHECK-MIPS1: bc1t %tmp = load double* @d2, align 8, !tbaa !0 %tmp1 = load double* @d3, align 8, !tbaa !0 %cmp = fcmp ogt double %tmp, %tmp1 |