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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/PowerPC/atomic-2.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/PowerPC/atomic-2.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/atomic-2.ll | 56 |
1 files changed, 55 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 9cb0fa5..9130921 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -march=ppc64 | FileCheck %s +; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-P7U +; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P7U define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { ; CHECK-LABEL: exchange_and_add: @@ -8,6 +10,22 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { ret i64 %tmp } +define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind { +; CHECK-LABEL: exchange_and_add8: +; CHECK-P7U: lbarx + %tmp = atomicrmw add i8* %mem, i8 %val monotonic +; CHECK-P7U: stbcx. + ret i8 %tmp +} + +define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind { +; CHECK-LABEL: exchange_and_add16: +; CHECK-P7U: lharx + %tmp = atomicrmw add i16* %mem, i16 %val monotonic +; CHECK-P7U: sthcx. + ret i16 %tmp +} + define i64 @exchange_and_cmp(i64* %mem) nounwind { ; CHECK-LABEL: exchange_and_cmp: ; CHECK: ldarx @@ -18,6 +36,26 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind { ret i64 %tmp } +define i8 @exchange_and_cmp8(i8* %mem) nounwind { +; CHECK-LABEL: exchange_and_cmp8: +; CHECK-P7U: lbarx + %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic + %tmp = extractvalue { i8, i1 } %tmppair, 0 +; CHECK-P7U: stbcx. +; CHECK-P7U: stbcx. + ret i8 %tmp +} + +define i16 @exchange_and_cmp16(i16* %mem) nounwind { +; CHECK-LABEL: exchange_and_cmp16: +; CHECK-P7U: lharx + %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic + %tmp = extractvalue { i16, i1 } %tmppair, 0 +; CHECK-P7U: sthcx. +; CHECK-P7U: sthcx. + ret i16 %tmp +} + define i64 @exchange(i64* %mem, i64 %val) nounwind { ; CHECK-LABEL: exchange: ; CHECK: ldarx @@ -26,6 +64,22 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind { ret i64 %tmp } +define i8 @exchange8(i8* %mem, i8 %val) nounwind { +; CHECK-LABEL: exchange8: +; CHECK-P7U: lbarx + %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic +; CHECK-P7U: stbcx. + ret i8 %tmp +} + +define i16 @exchange16(i16* %mem, i16 %val) nounwind { +; CHECK-LABEL: exchange16: +; CHECK-P7U: lharx + %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic +; CHECK-P7U: sthcx. + ret i16 %tmp +} + define void @atomic_store(i64* %mem, i64 %val) nounwind { entry: ; CHECK: @atomic_store @@ -39,7 +93,7 @@ entry: define i64 @atomic_load(i64* %mem) nounwind { entry: ; CHECK: @atomic_load - %tmp = load atomic i64* %mem acquire, align 64 + %tmp = load atomic i64, i64* %mem acquire, align 64 ; CHECK-NOT: ldarx ; CHECK: ld ; CHECK: sync 1 |